公开(公告)号：US08786036B2

公开(公告)日：2014-07-22

申请号：US12930877

申请日：2011-01-19

Applicant: Wei Cao ,  Cheng T. Horng ,  Witold Kula ,  Chyu Jiuh Torng

Inventor： Wei Cao ,  Cheng T. Horng ,  Witold Kula ,  Chyu Jiuh Torng

IPC: H01L43/10 ,  H01L27/22

CPC classification number: H01L43/10 ,  G11C11/161 ,  H01L27/222 ,  H01L43/00 ,  H01L43/02 ,  H01L43/08

Abstract: A MTJ in an MRAM array is disclosed with a composite free layer having a lower crystalline layer contacting a tunnel barrier and an upper amorphous NiFeX layer for improved bit switching performance. The crystalline layer is Fe, Ni, or FEB with a thickness of at least 6 Angstroms which affords a high magnetoresistive ratio. The X element in the NiFeX layer is Mg, Hf, Zr, Nb, or Ta with a content of 5 to 30 atomic % NiFeX thickness is preferably between 20 to 40 Angstroms to substantially reduce bit line switching current and number of shorted bits. In an alternative embodiments, the crystalline layer may be a Fe/NiFe bilayer. Optionally, the amorphous layer may have a NiFeM1/NiFeM2 configuration where M1 and M2 are Mg, Hf, Zr, Nb, or Ta, and M1 is unequal to M2. Annealing at 300° C. to 360° C. provides a high magnetoresistive ratio of about 150%.

Abstract translation: 公开了具有接触隧道势垒的较低结晶层和上部非晶NiFeX层的复合自由层的MRAM阵列中的MTJ，用于改善位切换性能。 结晶层是厚度至少为6埃的Fe，Ni或FEB，其具有高的磁阻比。 NiFeX层中的X元素为含有5〜30原子％NiFeX厚度的Mg，Hf，Zr，Nb或Ta优选为20〜40埃，以显着降低位线切换电流和短路位数。 在替代实施例中，结晶层可以是Fe / NiFe双层。 可选地，非晶层可以具有其中M1和M2是Mg，Hf，Zr，Nb或Ta的NiFeM1 / NiFeM2构型，M1不等于M2。 在300℃至360℃退火，提供约150％的高磁阻比。

公开(公告)号：US08780497B2

公开(公告)日：2014-07-15

申请号：US13493652

申请日：2012-06-11

Applicant: Yoshitaka Sasaki ,  Hiroyuki Ito ,  Kazuki Sato ,  Seiichiro Tomita ,  Hironori Araki ,  Tatsuya Shimizu

Inventor： Yoshitaka Sasaki ,  Hiroyuki Ito ,  Kazuki Sato ,  Seiichiro Tomita ,  Hironori Araki ,  Tatsuya Shimizu

IPC: G11B5/17

CPC classification number: G11B5/17 ,  G11B5/1278 ,  G11B5/3116 ,  G11B5/3123

Abstract: A magnetic head includes first and second coils, a main pole, a write shield, a return path section, and a core part. The return path section includes a yoke part magnetically connected to the write shield, and a coupling part located away from a medium facing surface and magnetically coupling the yoke part and the main pole to each other. The first coil is located on the front side in the direction of travel of a recording medium relative to the main pole and wound around the coupling part. The core part is located farther from the medium facing surface than is the coupling part, and is magnetically connected to the main pole. The second coil is located on the front side in the direction of travel of the recording medium relative to the main pole and wound around the core part.

Abstract translation: 磁头包括第一和第二线圈，主极，写入屏蔽，返回路径部分和核心部分。 返回路径部包括磁性地连接到写入屏蔽的轭部，以及远离介质面的表面并且将轭部和主极彼此磁耦合的耦合部。 第一线圈位于记录介质相对于主极的行进方向的前侧，并缠绕在联接部上。 核心部分位于与介质相对表面比耦合部分更远的位置，并且与主极磁性连接。 第二线圈位于记录介质相对于主极的行进方向的前侧，并缠绕在芯部上。

公开(公告)号：US08773803B2

公开(公告)日：2014-07-08

申请号：US13654490

申请日：2012-10-18

Applicant: Headway Technologies, Inc.

Inventor： Xuhui Jin ,  Hiroyuki Ito ,  Shigeki Tanemura ,  Dayu Zhou

IPC: G11B5/02

CPC classification number: G11B5/314 ,  G11B5/3163 ,  G11B2005/0021

Abstract: Three structures, and processes for manufacturing them, that improve the performance of a TAMR feature in a magnetic write head are disclosed. This improvement is achieved by making the separation between the edge plasmon generator and the plasmon shield less than the separation between the edge plasmon generator and the optical wave-guide.

Abstract translation: 公开了三种结构及其制造方法，其改进磁写头中的TAMR特征的性能。 这种改进通过使边缘等离子体发生器和等离子体屏蔽之间的分离小于边缘等离子体发生器和光波导之间的间隔来实现。

公开(公告)号：US08755150B2

公开(公告)日：2014-06-17

申请号：US14077164

申请日：2013-11-11

Applicant: Headway Technologies, Inc.

Inventor： Wenyu Chen ,  Joe Smyth

IPC: G11B5/127

CPC classification number: G11B5/399 ,  G11B5/1278 ,  G11B5/314 ,  G11B5/3146 ,  G11B2005/0024

Abstract: A design is disclosed for a microwave assisted magnetic recording device wherein direct current and rf current are simultaneously injected from a bias tee into a spin transfer oscillator (STO) between a main pole and write shield to improve the assist process. The STO oscillation layer (OL) has a large angle magnetization oscillation frequency that is locked to a magnetic medium bit resonance frequency f0 when the rf current has a frequency f=f0 and a threshold current density is applied. Alternatively, the OL magnetization oscillation frequency may be adjusted closer to f0 to improve the assist process. A third advantage is lowering the threshold current density when both direct current and rf current are injected into the STO during a write process. The main pole is grounded when direct current and rf current are injected into a write shield.

Abstract translation: 公开了一种用于微波辅助磁记录装置的设计，其中直流电流和射频电流同时从偏置三通管注入主极和写屏蔽之间的自旋转移振荡器（STO），以改善辅助过程。 STO振荡层（OL）具有大的角度磁化振荡频率，当rf电流具有频率f = f0并施加阈值电流密度时，其被锁定到磁介质位谐振频率f0。 或者，可以将OL磁化振荡频率调整为更接近于f0，以改善辅助处理。 第三个优点是在写入过程中将直流和直流电流都注入到STO中时降低阈值电流密度。 当直流电流和rf电流注入写入屏蔽时，主极接地。

公开(公告)号：US08755149B2

公开(公告)日：2014-06-17

申请号：US13620764

申请日：2012-09-15

Applicant: Suping Song ,  Lijie Guan ,  Tai Min ,  Yuhui Tang

Inventor： Suping Song ,  Lijie Guan ,  Tai Min ,  Yuhui Tang

IPC: G11B5/127

CPC classification number: G11B5/315 ,  G11B5/1278 ,  G11B5/3116 ,  G11B5/3163

Abstract: A magnetic recording head is fabricated with a pole tip shielded laterally on its sides by a pair of symmetrically disposed side shields formed of porous heterogeneous material that contains non-magnetic inclusions. The non-magnetic inclusions, when properly incorporated within the magnetic matrix of the shields, promote the formation of flux loops within the shields that have portions that are parallel to the ABS and do not display locally disorganized and dynamic regions of flux during the creation of magnetic transitions within the recording medium by the magnetic pole. These flux loop portions, combine with the magnetic flux emerging from the main pole to create a net writing field that significantly reduces adjacent track erasures (ATE) and wide area erasures (WATE).

Abstract translation: 制造磁记录头，其极侧通过由包含非磁性夹杂物的多孔异质材料形成的一对对称设置的侧屏蔽侧向屏蔽。 当非磁性夹杂物适当地并入屏蔽体的磁矩阵中时，促进在屏蔽体内形成具有与ABS平行的部分的磁通环，并且在创建过程中不显示局部无组织和动态的磁通区域 通过磁极在记录介质内的磁转变。 这些磁通回路部分与从主极产生的磁通相结合，形成一个净写入场，显着地减少了相邻轨道擦除（ATE）和广域擦除（WATE）。

公开(公告)号：US08747629B2

公开(公告)日：2014-06-10

申请号：US12284454

申请日：2008-09-22

Applicant: Hui-Chuan Wang ,  Tong Zhao ,  Min Li ,  Kunliang Zhang

Inventor： Hui-Chuan Wang ,  Tong Zhao ,  Min Li ,  Kunliang Zhang

IPC: C23C14/00 ,  C23C14/32 ,  G11B5/33 ,  G11B5/127

CPC classification number: G11B5/3909 ,  B82Y10/00 ,  B82Y25/00 ,  G01R33/098 ,  G11B5/33 ,  G11B5/3929 ,  G11B2005/3996 ,  Y10T428/1114

Abstract: A TMR sensor with a free layer having a FL1/FL2/FL3 configuration is disclosed in which FL1 is FeCo or a FeCo alloy with a thickness between 2 and 15 Angstroms. The FL2 layer is made of CoFeB or a CoFeB alloy having a thickness from 2 to 10 Angstroms. The FL3 layer is from 10 to 100 Angstroms thick and has a negative λ to offset the positive λ from FL1 and FL2 layers and is comprised of CoB or a CoBQ alloy where Q is one of Ni, Mn, Tb, W, Hf, Zr, Nb, and Si. Alternatively, the FL3 layer may be a composite such as CoB/CoFe, (CoB/CoFe)n where n is ≧2 or (CoB/CoFe)m/CoB where m is ≧1. The free layer described herein affords a high TMR ratio above 60% while achieving low values for λ (

Abstract translation: 公开了具有FL1 / FL2 / FL3结构的自由层的TMR传感器，其中FL1是FeCo或厚度在2和15埃之间的FeCo合金。 FL2层由厚度为2〜10埃的CoFeB或CoFeB合金制成。 FL3层的厚度为10〜100埃，并且具有负λ以从FL1和FL2层偏移正的λ，由CoB或CoBQ合金组成，其中Q是Ni，Mn，Tb，W，Hf，Zr ，Nb和Si。 或者，FL3层可以是其中n为≥2的CoB / CoFe（CoB / CoFe）n或（CoB / CoFe）m / CoB（其中m为≥1）的复合物。 此处描述的自由层提供高于60％的高TMR比，同时实现λ（<5×10-6），RA（1.5欧姆/μm2）和Hc（<6Oe）的低值。

公开(公告)号：US08726491B2

公开(公告)日：2014-05-20

申请号：US13373128

申请日：2011-11-04

Applicant: Cheng T. Horng ,  Ru-Ying Tong

Inventor： Cheng T. Horng ,  Ru-Ying Tong

IPC: G11B5/127 ,  H04R31/00

CPC classification number: G01R33/098 ,  G01R33/1284 ,  G11C11/161 ,  H01L43/08 ,  H01L43/10 ,  Y10T29/49032 ,  Y10T29/49043 ,  Y10T29/49044 ,  Y10T29/49046 ,  Y10T29/49048 ,  Y10T29/49052 ,  Y10T428/1107 ,  Y10T428/1114 ,  Y10T428/1121 ,  Y10T428/1129 ,  Y10T428/1136 ,  Y10T428/1143

Abstract: A dual spin filter that minimizes spin-transfer magnetization switching current (Jc) while achieving a high dR/R in STT-RAM devices is disclosed. The bottom spin valve has a MgO tunnel barrier layer formed with a natural oxidation process to achieve low RA, a CoFe/Ru/CoFeB—CoFe pinned layer, and a CoFeB/FeSiO/CoFeB composite free layer with a middle nanocurrent channel (NCC) layer to minimize Jc0. The NCC layer may have be a composite wherein conductive M(Si) grains are magnetically coupled with adjacent ferromagnetic layers and are formed in an oxide, nitride, or oxynitride insulator matrix. The upper spin valve has a Cu spacer to lower the free layer damping constant. A high annealing temperature of 360° C. is used to increase the MR ratio above 100%. A Jc0 of less than 1×106 A/cm2 is expected based on quasistatic measurements of a MTJ with a similar MgO tunnel barrier and composite free layer.

Abstract translation: 公开了在STT-RAM器件中实现高dR / R的同时使自旋迁移磁化开关电流（Jc）最小化的双自旋滤波器。 底部自旋阀具有通过自然氧化工艺形成的MgO隧道阻挡层，以实现低RA，CoFe / Ru / CoFeB-CoFe钉扎层和具有中等纳米通道（NCC）的CoFeB / FeSiO / CoFeB复合材料自由层， 层以最小化Jc0。 NCC层可以是其中导电M（Si）晶粒与相邻铁磁层磁耦合并且形成在氧化物，氮化物或氧氮化物绝缘体基体中的复合材料。 上自旋阀具有Cu间隔物以降低自由层阻尼常数。 使用360℃的高退火温度将MR比提高到100％以上。 基于具有类似的MgO隧道势垒和复合自由层的MTJ的准静态测量，预期小于1×106A / cm 2的Jc0。

公开(公告)号：US20140119105A1

公开(公告)日：2014-05-01

申请号：US13660176

申请日：2012-10-25

Applicant: HEADWAY TECHNOLOGIES, INC.

Inventor： Guenole Jan ,  PoKang Wang

IPC: G11C11/02

CPC classification number: G11C11/16 ,  G11C11/1673 ,  G11C2207/002

Abstract: A structure and method is described for an adaptive reference used in reading magnetic tunneling memory cells. A collection of magnetic tunneling memory cells are used to form a reference circuit and are coupled in parallel between circuit ground and a reference input to a sense amplifier. Each of the magnetic memory cells used to form the reference circuit are programmed to a magnetic parallel state or a magnetic anti-parallel state, wherein each different state produces a different resistance. By varying the number of parallel states in comparison to the anti-parallel states, where each of the two sates produce a different resistance, the value of the reference circuit resistance can be adjusted to adapt to the resistance characteristics of a magnetic memory data cell to produce a more reliable read of the data programmed into the magnetic memory data cell.

Abstract translation: 描述了用于读磁磁隧道存储单元的自适应参考的结构和方法。 使用磁隧道存储单元的集合来形成参考电路，并且在电路接地和参考输入之间并联耦合到读出放大器。 用于形成参考电路的每个磁存储单元被编程为磁性平行状态或磁反向平行状态，其中每个不同的状态产生不同的电阻。 通过与反并联状态相比，通过改变并联状态的数量，其中两个状态中的每一个产生不同的电阻，可以调整参考电路电阻的值以适应磁存储器数据单元的电阻特性 对写入磁存储器数据单元的数据进行更可靠的读取。

公开(公告)号：US08710641B2

公开(公告)日：2014-04-29

申请号：US13422723

申请日：2012-03-16

Applicant: Yoshitaka Sasaki ,  Hiroyuki Ito ,  Atsushi Iijima

Inventor： Yoshitaka Sasaki ,  Hiroyuki Ito ,  Atsushi Iijima

IPC: H01L23/02 ,  H01L29/40

CPC classification number: H01L24/94 ,  G11C29/006 ,  G11C29/82 ,  H01L22/22 ,  H01L24/24 ,  H01L24/25 ,  H01L24/32 ,  H01L24/82 ,  H01L24/83 ,  H01L24/92 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/24147 ,  H01L2224/25175 ,  H01L2224/32145 ,  H01L2224/821 ,  H01L2224/83005 ,  H01L2224/9202 ,  H01L2224/94 ,  H01L2225/06524 ,  H01L2225/06551 ,  H01L2225/06565 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/07802 ,  H01L2224/03 ,  H01L2224/83 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A main package includes a plurality of stacked semiconductor chips and a plurality of first terminals associated with different ones of the semiconductor chips. An additional package includes an additional semiconductor chip and at least one second terminal electrically connected to the additional semiconductor chip. The additional semiconductor chip is to substitute for one of the plurality of semiconductor chips in the main package. The main package and the additional package are arranged in one of a plurality of relative positional relationships that is selected according to which one of the plurality of semiconductor chips in the main package is to be substituted with the additional semiconductor chip.

Abstract translation: 主封装包括多个堆叠的半导体芯片和与不同的半导体芯片相关联的多个第一端子。 附加封装包括附加的半导体芯片和电连接到附加半导体芯片的至少一个第二端子。 附加的半导体芯片用于代替主封装中的多个半导体芯片中的一个。 主包装和附加包装被布置成根据主包装中的多个半导体芯片中的哪一个被附加的半导体芯片代替的多个相对位置关系中的一个。

公开(公告)号：US08691102B1

公开(公告)日：2014-04-08

申请号：US13731754

申请日：2012-12-31

Applicant: Hironori Araki ,  Yoshitaka Sasaki ,  Hiroyuki Ito ,  Yukinori Ikegawa ,  Seiichiro Tomita ,  Shigeki Tanemura

Inventor： Hironori Araki ,  Yoshitaka Sasaki ,  Hiroyuki Ito ,  Yukinori Ikegawa ,  Seiichiro Tomita ,  Shigeki Tanemura

IPC: C03C15/00

CPC classification number: G11B5/314 ,  G11B5/3163 ,  G11B5/6088 ,  G11B2005/0021

Abstract: A method of manufacturing a plasmon generator includes the steps of: forming an etching mask on a dielectric layer; forming an accommodation part by etching the dielectric layer using the etching mask; and forming the plasmon generator to be accommodated in the accommodation part. The step of forming the etching mask includes the steps of: forming a patterned layer on an etching mask material layer, the patterned layer having a first opening that has a sidewall; forming a structure by forming an adhesion film on the sidewall, the structure having a second opening smaller than the first opening; and etching a portion of the etching mask material layer exposed from the second opening.

Abstract translation: 一种制造等离子体发生器的方法包括以下步骤：在电介质层上形成蚀刻掩模; 通过使用蚀刻掩模蚀刻电介质层来形成容纳部分; 以及形成要容纳在容纳部分中的等离子体发生器。 形成蚀刻掩模的步骤包括以下步骤：在蚀刻掩模材料层上形成图案化层，所述图案化层具有具有侧壁的第一开口; 通过在侧壁上形成粘合膜来形成结构，该结构具有比第一开口小的第二开口; 并蚀刻从第二开口露出的蚀刻掩模材料层的一部分。