公开(公告)号：US12095458B2

公开(公告)日：2024-09-17

申请号：US17825378

申请日：2022-05-26

申请人： Samsung Electronics Co., Ltd.

发明人： Umamaheswara Reddy Katta ,  Tamal Das

IPC分类号： H03K19/0185 ,  H03K19/017 ,  H03K19/094 ,  H03K19/20

CPC分类号： H03K19/01855 ,  H03K19/01742 ,  H03K19/0941 ,  H03K19/20

摘要： A method, implemented in a serializer for quarter rate serialization, is disclosed. The method includes receiving a plurality of in-phase and quarter-phase clock signals defining a quarter phase clock. The method includes receiving a quarter rate data input and sequentially outputting data in accordance with the quarter phase clock. The method includes receiving at least one data input from amongst the quarter rate input and outputting a first logical output in accordance with the in-phase clock signal and the quarter-phase clock signal. The method includes receiving said at least one data input and outputting a second logical output in accordance a complementary in-phase clock signal and a complementary quarter-phase clock signal. The method includes outputting, an output associated with the branch.

公开(公告)号：US12040795B2

公开(公告)日：2024-07-16

申请号：US17413791

申请日：2019-12-10

申请人： Semiconductor Energy Laboratory Co., Ltd.

发明人： Hiroki Inoue ,  Munehiro Kozuma ,  Takeshi Aoki ,  Shuji Fukai ,  Fumika Akasawa ,  Shintaro Harada ,  Sho Nagao

IPC分类号： H03K19/094 ,  H01L27/06

CPC分类号： H03K19/094 ,  H01L27/0629

摘要： A semiconductor device using unipolar transistors, in which high and low levels are expressed using high and low power supply potentials, is provided. The semiconductor device includes four transistors, two capacitors, two wirings, two input terminals, and an output terminal. A source or a drain of the first transistor and a source or a drain of the fourth transistor are electrically connected to the first wiring. A gate of the fourth transistor is electrically connected to the first input terminal, and a gate of the second transistor is electrically connected to the second input terminal. A source or a drain of the second transistor and a source or a drain of the third transistor are electrically connected to the second wiring. The first transistor, the second transistor, and the two capacitors are electrically connected to the output terminal.

公开(公告)号：US20240178841A1

公开(公告)日：2024-05-30

申请号：US18507524

申请日：2023-11-13

申请人： Nokia Solutions and Networks Oy

发明人： Mustafa SAYGINER

IPC分类号： H03K19/0185 ,  H03K19/094

CPC分类号： H03K19/018585 ,  H03K19/09425

摘要： Disclosed is a method comprising determining that a signal is to be provided to a beamformer integrated circuit using a control interface associated with the beamformer integrated circuit, identifying, within, at least one memory, a unique address of the beamformer integrated circuit, wherein the beamformer integrated circuit is aware of own unique address based on a set state of an address pin of the beamformer integrated circuit, wherein the set state of the address pin is one of at least three available set states, the set state being provided as an input to three logical buffers electrically coupled to the beamformer integrated circuit, and outputs from the three logical buffers being combined using a logical encoder that generates the unique address, and providing the signal to the beamformer integrated circuit using the unique address.

公开(公告)号：US11935899B2

公开(公告)日：2024-03-19

申请号：US17047740

申请日：2019-04-08

申请人： SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

发明人： Takahiko Ishizu ,  Seiichi Yoneda

IPC分类号： H03K19/00 ,  H01L27/12 ,  H01L29/24 ,  H03K19/003 ,  H03K19/017 ,  H03K19/094 ,  H03K19/20

CPC分类号： H01L27/124 ,  H01L27/1259 ,  H01L29/24 ,  H03K19/00315 ,  H03K19/017 ,  H03K19/0941 ,  H03K19/20

摘要： A semiconductor device capable of stable operation with low power consumption is provided. A logic circuit having a circuit configuration using a transistor including an oxide semiconductor in a channel formation region is included. The logic circuit is a two-input/two-output two-wire logic circuit. Transistors included in the logic circuit each include a gate and a back gate. An input terminal is electrically connected to one of a gate and a back gate of a transistor electrically connected to a wiring for supplying a high power supply potential. An output terminal is connected to the other of the gate and the back gate of the transistor electrically connected to the wiring for supplying a high power supply potential. An output terminal is electrically connected to one of a source and a drain of a transistor electrically connected to a wiring for supplying a low power supply potential. A gate or a back gate of the transistor electrically connected to the wiring for supplying a low power supply potential is electrically connected to an input terminal.

公开(公告)号：US11838021B1

公开(公告)日：2023-12-05

申请号：US17229277

申请日：2021-04-13

申请人： Matthew Barlow ,  James A. Holmes

发明人： Matthew Barlow ,  James A. Holmes

IPC分类号： H03K19/094 ,  H03K19/09

CPC分类号： H03K19/09403 ,  H03K19/09 ,  H03K19/09425

摘要： An improved electrical circuit for logic output level shifting using SiC JFETs with resistors on the input, inverting, stage and using diode degenerated JFET sources in the output stage.

公开(公告)号：US20230170907A1

公开(公告)日：2023-06-01

申请号：US18060223

申请日：2022-11-30

申请人： POSTECH RESEARCH AND BUSINESS DEVELOPMENT FOUNDATION

发明人： Seokhyeong KANG ,  Youngchang CHOI ,  Sunmean KIM ,  Kyongsu LEE

IPC分类号： H03K19/094 ,  H03K19/0185 ,  H03K19/0944 ,  G11C11/41

CPC分类号： H03K19/09425 ,  H03K19/0185 ,  H03K19/0944 ,  G11C11/41

摘要： Disclosed is an inverter which includes a first P-MOS transistor connected between a node receiving a drain voltage and a first path node and operated based on an input voltage, a first N-MOS transistor connected between the first path node and an output terminal outputting an output voltage and operated based on the drain voltage, a second P-MOS transistor connected between the output terminal and a second path node and operated based on a ground voltage, a second N-MOS transistor connected between the second path node and a node receiving the ground voltage and operated based on the input voltage, a third P-MOS transistor connected between the first path node and the second path node and operated based on the input voltage, and a third N-MOS transistor connected between the first path node and the second path node and operated based on the input voltage.

公开(公告)号：US11632111B1

公开(公告)日：2023-04-18

申请号：US17518029

申请日：2021-11-03

申请人： Hamilton Sundstrand Corporation

发明人： John A. Dickey

IPC分类号： H03K19/094 ,  H03K19/003 ,  H03K19/20

摘要： A control system is provides that includes a logic gate generating an output state signal, and first and second redundant controllers, wherein the first controller is configured to output a first state signal to a first input of the logic gate, and the second controller is configured to output a second state signal to a second input of the logic gate, and wherein the first controller is configured to receive an impedance isolated feedback signal corresponding to the second state signal from the second controller, and the second controller is configured to receive an impedance isolated feedback signal corresponding to the first state signal from the first controller, so that each controller can determine whether both inputs to the logic gate match one another.

公开(公告)号：US11621703B2

公开(公告)日：2023-04-04

申请号：US16900854

申请日：2020-06-12

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

发明人： Ta-Pen Guo ,  Chi-Lin Liu ,  Shang-Chih Hsieh ,  Jerry Chang-Jui Kao ,  Li-Chun Tien ,  Lee-Chung Lu

IPC分类号： H03K19/00 ,  H03K3/0233 ,  H03K23/58 ,  H03K19/094 ,  H03K3/01 ,  H01L27/02 ,  H03K3/356 ,  H03K3/3562 ,  H01L27/118 ,  H01L27/092 ,  H01L27/12

摘要： A semiconductor standard cell of a flip-flop circuit includes semiconductor fins extending substantially parallel to each other along a first direction, electrically conductive wirings disposed on a first level and extending substantially parallel to each other along the first direction, and gate electrode layers extending substantially parallel to a second direction substantially perpendicular to the first direction and formed on a second level different from the first level. The flip-flop circuit includes transistors made of the semiconductor fins and the gate electrode layers, receives a data input signal, stores the data input signal, and outputs a data output signal indicative of the stored data in response to a clock signal, the clock signal is the only clock signal received by the semiconductor standard cell, and the data input signal, the clock signal, and the data output signal are transmitted among the transistors through at least the electrically conductive wirings.

公开(公告)号：US11411561B2

公开(公告)日：2022-08-09

申请号：US17285536

申请日：2019-08-09

申请人： SONY SEMICONDUCTOR SOLUTIONS CORPORATION

发明人： Takanori Saeiki

IPC分类号： H03K3/00 ,  H03K5/02 ,  H03K17/687 ,  H03K19/094 ,  H02M1/08 ,  H03K19/0185 ,  H03K3/356 ,  H03K17/16

摘要： A signal is caused to have a small amplitude without increasing a voltage source, and power consumption is reduced. A semiconductor circuit includes a driver, and a pulse control circuit that controls the driver. The driver has a configuration in which first and second transistors are connected. The pulse control circuit supplies a first control signal to the first transistor, and supplies a second control signal to the second transistor. The first and second control signals to be supplied from the pulse control circuit are different in a pulse width from each other. Therefore, the pulse control circuit reduces an output amplitude of the driver.

公开(公告)号：US11329649B2

公开(公告)日：2022-05-10

申请号：US17315391

申请日：2021-05-10

申请人： REALTEK SEMICONDUCTOR CORPORATION

发明人： Ya-Hsuan Sung

IPC分类号： H03K19/017 ,  H03K19/17736 ,  H03K19/094 ,  H03K19/17784

摘要： A port controller device includes a pull-up resistor, a switching circuit, an enabling circuitry, and a protection circuitry. The pull-up resistor is configured to be coupled to a port, in which the port is configured to be coupled to a channel configuration pin of an electronic device. The switching circuit is configured to selectively transmit a supply voltage to the port via the pull-up resistor according to a first control signal, and turn off a signal path between the pull-up resistor and the port according to a second control signal. The enabling circuitry is configured to generate the first control signal according to an enable signal and the supply voltage. The protection circuitry is configured to generate the second control signal in response to a voltage from the port when the supply voltage is not powered, in order to limit a current from the port.