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    FPGA having a Virtual Array of Logic Tiles, and Method of Configuring and Operating Same
    2.
    发明申请
    FPGA having a Virtual Array of Logic Tiles, and Method of Configuring and Operating Same 审中-公开

    公开(公告)号：US20180343010A1

    公开(公告)日：2018-11-29

    申请号：US15975037

    申请日：2018-05-09

    申请人： Flex Logix Technologies, Inc.

    发明人： Anthony Kozaczuk ,  Cheng C. Wang ,  Abhijit M. Abhyankar

    IPC分类号： H03K19/177 ,  G06F17/50

    CPC分类号： H03K19/1776 ,  G06F17/5054 ,  G06F17/5068 ,  H03K19/17704 ,  H03K19/17728 ,  H03K19/17736

    摘要： An integrated circuit comprising a physical array of logic tiles, wherein each logic tile includes a perimeter and a plurality of external I/O disposed in a layout on the perimeter of the logic tile wherein the layout of the external I/O of each logic tile is identical. The physical array includes a first virtual array of logic tiles, programmed to perform data processing operations, including a first plurality of logic tiles of the physical array. The physical array also includes a second virtual array of logic tiles, programmed to perform second operations, including a second plurality of logic tiles of the physical array. The logic tiles of the second plurality are different from the logic tiles of the first plurality. In one embodiment, performance of the data processing operations of the first virtual array is independent from performance of the second operations of the second virtual array.

    SCALABLE CROSSBAR APPARATUS AND METHOD FOR ARRANGING CROSSBAR CIRCUITS
    4.
    发明申请
    SCALABLE CROSSBAR APPARATUS AND METHOD FOR ARRANGING CROSSBAR CIRCUITS 有权
    可调节的横梁装置和安装横梁电路的方法

    公开(公告)号：US20160380629A1

    公开(公告)日：2016-12-29

    申请号：US14751060

    申请日：2015-06-25

    申请人： Intel Corporation

    发明人： Gregory K. Chen ,  Mark A. Anders ,  Himanshu Kaul

    IPC分类号： H03K19/00 ,  H03K19/177

    CPC分类号： H03K19/0008 ,  H03K19/17704 ,  H03K19/17744

    摘要： Described is an apparatus (e.g., a router) which comprises: multiple ports; and a plurality of crossbar circuits arranged such that at least one crossbar circuit receives all interconnects associated with a data bit of the multiple ports and is operable to re-route signals on those interconnects.

    摘要翻译： 描述了一种装置（例如，路由器），其包括：多个端口; 以及布置成使得至少一个交叉电路接收与多个端口的数据位相关联的所有互连并且可操作以在那些互连上重新路由信号的多个交叉电路电路。

    Configurable IC having a routing fabric with storage elements
    6.
    发明授权
    Configurable IC having a routing fabric with storage elements 有权

    公开(公告)号：US09490814B2

    公开(公告)日：2016-11-08

    申请号：US14246955

    申请日：2014-04-07

    申请人： Altera Corporation

    发明人： Steven Teig ,  Herman Schmit ,  Randy Renfu Huang

    IPC分类号： H03K19/177

    CPC分类号： H03K19/17704 ,  H03K19/17736

    摘要： Some embodiments provide a configurable IC that includes a configurable routing fabric with storage elements. In some embodiments, the routing fabric provides a communication pathway that routes signals to and from source and destination components. The routing fabric of some embodiments provides the ability to selectively store the signals passing through the routing fabric within the storage elements of the routing fabric. In this manner, a source or destination component continually performs operations (e.g., computational or routing) irrespective of whether a previous signal from or to such a component is stored within the routing fabric. The source and destination components include configurable logic circuits, configurable interconnect circuits, and various other circuits that receive or distribute signals throughout the configurable IC.

    Programmable interconnection device
    7.
    发明授权
    Programmable interconnection device 有权
    可编程互连设备

    公开(公告)号：US09362918B2

    公开(公告)日：2016-06-07

    申请号：US14780431

    申请日：2014-03-25

    申请人： NANOXPLORE

    发明人： Olivier Lepape

    IPC分类号： H03K19/177

    CPC分类号： H03K19/17744 ,  H03K19/17704 ,  H03K19/17736 ,  H03K19/1776

    摘要： The invention relates to a programmable interconnection device, comprising: first rows of functional blocks, each functional block having inputs and outputs; second rows of programmable interconnection cells; horizontal connections, each connecting a programmable interconnection cell of the second row with only one other cell of that row; and connection bundles comprising transverse connections connecting a given programmable interconnection cell with functional blocks of the neighboring first row; the cells being suitable together for interconnecting the inputs and the outputs of each functional block of each first row with the outputs and the inputs of all of the other functional blocks of the same row.

    摘要翻译： 本发明涉及一种可编程互连装置，包括：第一排功能块，每个功能块具有输入和输出; 第二排可编程互连电池; 水平连接，每个连接第二行的可编程互连单元仅与该行的另一个单元; 以及连接束，其包括将给定可编程互连单元与相邻第一行的功能块连接的横向连接; 这些单元适合于一起，用于将每个第一行的每个功能块的输入和输出与同一行的所有其他功能块的输出和输入相互连接。

    SYSTEM LEVEL INTERCONNECT WITH PROGRAMMABLE SWITCHING
    8.
    发明申请
    SYSTEM LEVEL INTERCONNECT WITH PROGRAMMABLE SWITCHING 有权
    系统级别与可编程开关互连

    公开(公告)号：US20160105186A1

    公开(公告)日：2016-04-14

    申请号：US14968247

    申请日：2015-12-14

    申请人： Cypress Semiconductor Corporation

    发明人： Bert S. Sullam ,  Warren S. Snyder ,  Haneef D. Mohammed

    IPC分类号： H03K19/177

    CPC分类号： H03K19/17744 ,  H03K19/173 ,  H03K19/177 ,  H03K19/17704 ,  H03K19/1776

    摘要： Different functional elements are all located on a same integrated circuit wherein at least one of the functional elements comprises a micro-controller. Configuration registers or configuration memory in the integrated circuit store configuration values loaded by the micro-controller. Connectors are configured to connect the integrated circuit to external signals A system level interconnect also located in the integrated circuit programmably connects together the different functional elements and different connectors according to the configuration values loaded into the configuration registers.

    摘要翻译： 不同的功能元件都位于相同的集成电路中，其中至少一个功能元件包括微控制器。 集成电路中的配置寄存器或配置存储器存储由微控制器加载的配置值。 连接器被配置为将集成电路连接到外部信号。还集成电路中的系统级互连可根据加载到配置寄存器中的配置值可编程地将不同功能元件和不同连接器连接在一起。

    RUNTIME LOADING OF CONFIGURATION DATA IN A CONFIGURABLE IC
    9.
    发明申请
    RUNTIME LOADING OF CONFIGURATION DATA IN A CONFIGURABLE IC 审中-公开
    在配置IC中运行配置数据

    公开(公告)号：US20160028399A1

    公开(公告)日：2016-01-28

    申请号：US14664755

    申请日：2015-03-20

    申请人： Altera Corporation

    发明人： Brad Hutchings ,  Jason Redgrave ,  Teju Khubchandani ,  Herman Schmit ,  Steven Teig

    IPC分类号： H03K19/173 ,  H03K19/177

    CPC分类号： H03K19/1731 ,  H03K19/177 ,  H03K19/17704 ,  H03K19/17736 ,  H03K19/17748 ,  H03K19/17756 ,  H03K19/17764

    摘要： Some embodiments of the invention provide a configurable integrated circuit (IC) that has several configurable circuits for configurably performing different operations. During the operation of the IC, each particular configurable circuit performs a particular operation that is specified by a particular configuration data set for the particular configurable circuit. While the IC operates and a first set of configurable circuits performs a first set of operations, configuration data is loaded from the outside of the IC for configuring a second set of configurable circuits. In some embodiments, the configurable IC includes a configuration network for rapid loading configuration data in the IC from outside of the IC. In some of these embodiments, the configuration network is a pipelined network. Also, the IC of some embodiments includes a configuration controller for retrieving configuration data from outside of the IC, formulating configuration data sets, and routing the configuration data sets to the second set of configurable circuits over the configuration network.

    摘要翻译： 本发明的一些实施例提供了一种可配置集成电路（IC），其具有用于可配置地执行不同操作的多个可配置电路。 在IC的操作期间，每个特定可配置电路执行由针对特定可配置电路的特定配置数据集指定的特定操作。 当IC操作并且第一组可配置电路执行第一组操作时，从IC的外部加载配置数据，用于配置第二组可配置电路。 在一些实施例中，可配置IC包括用于从IC外部快速加载IC中的配置数据的配置网络。 在这些实施例中的一些实施例中，配置网络是流水线网络。 此外，一些实施例的IC包括用于从IC外部检索配置数据的配置控制器，配置数据组，以及通过配置网络将配置数据集路由到第二组可配置电路。