公开(公告)号：US20240355790A1

公开(公告)日：2024-10-24

申请号：US18758503

申请日：2024-06-28

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： Tae Jin KONG ,  Dae Hyun KIM ,  Myeong Hee KIM ,  Veidhes BASRUR ,  Je Won YOO ,  Xinxing LI ,  Hee Keun LEE ,  Bek Hyun LIM ,  Hyun Min CHO ,  Chang Il TAE

IPC: H01L25/075 ,  B82B3/00 ,  G09G3/32 ,  H01L27/12 ,  H01L33/00 ,  H01L33/24 ,  H01L33/36 ,  H01L33/44 ,  H01L33/62

CPC classification number: H01L25/0753 ,  B82B3/0052 ,  H01L27/1214 ,  H01L33/0062 ,  H01L33/24 ,  H01L33/36 ,  H01L33/44 ,  H01L33/62 ,  G09G3/32 ,  G09G2300/0842 ,  H01L2933/0016 ,  H01L2933/0025

Abstract: A light emitting device includes first and second electrodes disposed on a substrate; an insulating layer disposed on the substrate and including a groove extending in a first direction intersecting with the first and the second electrodes, and first and second contact portions that expose areas of the first and the second electrodes; light emitting elements disposed in the groove between the first and the second electrodes, each including first and second ends electrically connected to the first and second electrodes, respectively; a first contact electrode electrically connected to the light emitting elements on the first ends, and electrically connected to the first electrode on the first contact portion; and a second contact electrode electrically connected to the light emitting elements on the second ends, and electrically connected to the second electrode on the second contact portion.

公开(公告)号：US12125943B2

公开(公告)日：2024-10-22

申请号：US18505348

申请日：2023-11-09

Applicant: EPISTAR CORPORATION

Inventor： Huan-Yu Lai ,  Li-Chi Peng

IPC: H01L33/14 ,  H01L33/00 ,  H01L33/04 ,  H01L33/06 ,  H01L33/30 ,  H01L33/32

CPC classification number: H01L33/145 ,  H01L33/0062 ,  H01L33/04 ,  H01L33/06 ,  H01L33/14 ,  H01L33/30 ,  H01L33/305 ,  H01L33/32 ,  H01L33/325

Abstract: A semiconductor device is provided. The semiconductor device includes a first semiconductor layer; a second semiconductor layer on the first semiconductor layer; an active region between the second semiconductor layer and the first semiconductor layer; an electron blocking structure between the active region and the second semiconductor layer; a first nitride semiconductor layer between the active region and the electron blocking structure; and a second nitride semiconductor layer between the electron blocking structure and the second semiconductor layer. The first nitride semiconductor layer includes a first indium content, a first aluminum content and a first conductivity-type dopant. The second nitride semiconductor layer includes a second indium content, a second aluminum content and a second conductivity-type dopant. The electron blocking structure includes a first semiconductor layer including a third indium content and a third aluminum content; wherein the third indium content is greater than the second indium content.

公开(公告)号：US20240347670A1

公开(公告)日：2024-10-17

申请号：US18683884

申请日：2022-08-16

Applicant: ams-OSRAM international GmbH

Inventor： Christoph Klemp ,  Stefan IIIek ,  Ines Pietzonka ,  Andreas Biebersdorf ,  Xue Wang

IPC: H01L33/14 ,  H01L33/00 ,  H01L33/02 ,  H01L33/06 ,  H01L33/30

CPC classification number: H01L33/14 ,  H01L33/0062 ,  H01L33/025 ,  H01L33/06 ,  H01L33/305

Abstract: In an embodiment a method includes providing a growth substrate layer, depositing a first doped [(AlxGa1-x)yIn1-y]zP1-z carrier transport layer on the substrate layer with x in a range of [0.5;1] along a growth direction, and depositing an active region along the growth direction, the active region for generating radiation and comprising a plurality of alternating [(AlaGa1-a)bIn1-b]cP1-c quantum well layers and [(AldGa1-d)eIn1-e]fP1-f barrier layers, wherein a is in a range of [0;0.5] and d is in a range of [0.45;1.0], wherein depositing of at least one of the barrier layer and/or the quantum well layer comprises doping with a dopant having a concentration in a range of 1e15 atoms/cm3 to 5e17 atoms/cm3, wherein the dopant is selected from at least one of the group consisting of Mg, Zn, Te and Si or depositing a second doped carrier transport [(AlxGa1-x)yIn1-y]zP1-z layer with x in a range of [0.45;1] along the growth direction.

公开(公告)号：US20240282886A1

公开(公告)日：2024-08-22

申请号：US18571570

申请日：2021-06-18

Applicant: ams-OSRAM Intemational GmbH

Inventor： Heng Wang

IPC: H01L33/06 ,  H01L33/00 ,  H01L33/24 ,  H01L33/30

CPC classification number: H01L33/06 ,  H01L33/0062 ,  H01L33/24 ,  H01L33/305

Abstract: In an embodiment an optoelectronic device includes a semiconductor body with a layer stack including a first n-doped layer, a quantum well structure arranged on the first n-doped layer, and a p-doped layer arranged on the quantum well structure, wherein the quantum well structure extends along a lateral plane within the first region of the layer stack, wherein the quantum well structure extends within the second region on an inclined surface of one of the n-doped layer and p-doped layer with regards to the lateral plane to the sidewall of the layer stack such that a thickness of the quantum well structure within the second region is smaller than a thickness of the quantum well structure within the first region, and wherein a doping concentration of the n-doped layer in the second region is lower that a doping concentration in the first region.

公开(公告)号：US20240266465A1

公开(公告)日：2024-08-08

申请号：US18636979

申请日：2024-04-16

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Joohun HAN ,  Junhee Choi ,  Nakhyun Kim ,  Dongho Kim ,  Jinjoo Park

IPC: H01L33/14 ,  H01L27/15 ,  H01L33/00 ,  H01L33/30

CPC classification number: H01L33/145 ,  H01L27/156 ,  H01L33/0062 ,  H01L33/0095 ,  H01L33/30

Abstract: A nanorod light emitting device, a method of manufacturing the same, and a display apparatus including the nanorod light emitting device are provided. The nanorod light emitting device includes a first semiconductor layer doped with a first conductivity type, a light emitting layer disposed on the first semiconductor layer, and a second semiconductor layer disposed on the light emitting layer and doped with a second conductivity type that is electrically opposite to the first conductivity type, wherein a distance between a lower surface of the first semiconductor layer and an upper surface of the second semiconductor layer is in a range of about 2 μm to about 10 μm, wherein a difference between a diameter of the upper surface of the second semiconductor layer and the lower surface of the first semiconductor layer is 10% or less of a diameter of the upper surface of the second semiconductor layer.

公开(公告)号：US12046700B2

公开(公告)日：2024-07-23

申请号：US18238390

申请日：2023-08-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Junhee Choi ,  Nakhyun Kim ,  Jinjoo Park ,  Joohun Han

IPC: H01L33/24 ,  H01L27/15 ,  H01L33/00 ,  H01L33/06 ,  H01L33/14 ,  H01L33/30 ,  H01L33/40

CPC classification number: H01L33/24 ,  H01L27/156 ,  H01L33/0025 ,  H01L33/0062 ,  H01L33/06 ,  H01L33/145 ,  H01L33/30 ,  H01L33/40

Abstract: Provided is a nanorod light-emitting device including a first semiconductor layer doped with a first conductive type impurity, an emission layer disposed above the first semiconductor layer, a second semiconductor layer disposed above the emission layer and doped with a second conductive type impurity that is electrically opposite to the first conductive type impurity, a conductive layer disposed between at least one of a center portion of a lower surface of the emission layer and the first semiconductor layer and a center portion of an upper surface of the emission layer and the second semiconductor layer, and a current blocking layer surrounding a sidewall of the conductive layer.

公开(公告)号：US20240222547A1

公开(公告)日：2024-07-04

申请号：US17924314

申请日：2022-07-20

Applicant: Shuzhou Everbright Photonics Co., ltd. ,  Everbright Institute of Semiconductor Photonics Co., Ltd.

Inventor： Jun WANG ,  Yudan Gou ,  Li Zhou ,  Yang Cheng ,  Shaoyang Tan ,  Lichen Zhang ,  Bo Li

IPC: H01L33/04 ,  H01L33/00 ,  H01L33/30

CPC classification number: H01L33/04 ,  H01L33/0062 ,  H01L33/30

Abstract: A multi-active area semiconductor structure and a method for manufacturing same. The multi-active area semiconductor structure includes: a (2k−1)th common confining layer arranged between a kth active layer and a kth tunnel junction and in contact with the kth tunnel junction; and a 2kth common confining layer arranged between the kth active layer and a (k+1)th tunnel junction and in contact with the kth tunnel junction, where a forbidden band width of a kth quantum well layer is less than both a forbidden band width of a kth first-semiconductor layer and a forbidden band width of a kth second-semiconductor layer; a total thickness of the (2k−1)th common confining layer and the 2kth common confining layer is greater than a critical optical field coupling thickness and less than or equal to twice the critical optical field coupling thickness; and a thickness of the kth quantum well layer is less than or equal to 1/10 of a thickness of the (2k−1)th common confining layer, and the thickness of the kth quantum well layer is less than or equal to 1/10 of a thickness of the 2kth common confining layer. The multi-active area semiconductor structure has effectively improved light-emission efficiency and reduced optical field crosstalk.

公开(公告)号：US20240204130A1

公开(公告)日：2024-06-20

申请号：US18537470

申请日：2023-12-12

Applicant: Commissariat à I'Énergie Atomique et aux Énergies Alternatives

Inventor： Ludovic Dupre ,  Carole Pernel

IPC: H01L33/00

CPC classification number: H01L33/0093 ,  H01L33/0062 ,  H01L2933/0016

Abstract: A method of manufacturing an electronic device comprising the following successive steps: a) forming a structure comprising a diode stack disposed on a first substrate, and a sacrificial layer of semiconductor material interposed between the first substrate and the diode stack; b) transferring the structure to a second substrate; and c) removing the first substrate by electropolishing the sacrificial layer by applying a bias voltage to the sacrificial layer via the diode stack.

公开(公告)号：US11996496B2

公开(公告)日：2024-05-28

申请号：US18053374

申请日：2022-11-08

Applicant: DOWA Electronics Materials Co., Ltd.

Inventor： Jumpei Yamamoto ,  Tetsuya Ikuta

IPC: H01L33/30 ,  H01L33/00 ,  H01L33/40 ,  H01L33/46 ,  H01L33/62

CPC classification number: H01L33/30 ,  H01L33/0062 ,  H01L33/40 ,  H01L33/46 ,  H01L33/62 ,  H01L2933/0016 ,  H01L2933/0025 ,  H01L2933/0066

Abstract: A semiconductor light-emitting device includes: a conductive support substrate; a metal layer comprising a reflective metal provided on the conductive support substrate; a semiconductor laminate provided on the metal layer, the semiconductor laminate being a stack of a plurality of InGaAsP-based III-V group compound semiconductor layers containing at least In and P; an n-type InGaAs contact layer provided on the semiconductor laminate; and an n-side electrode provided on the n-type InGaAs contact layer. A center emission wavelength of light emitted from the semiconductor laminate is 1000 to 2200 nm.

公开(公告)号：US11990563B2

公开(公告)日：2024-05-21

申请号：US17197326

申请日：2021-03-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Joohun Han ,  Junhee Choi ,  Nakhyun Kim ,  Dongho Kim ,  Jinjoo Park

IPC: H01L33/08 ,  H01L27/15 ,  H01L33/00 ,  H01L33/14 ,  H01L33/30

CPC classification number: H01L33/145 ,  H01L27/156 ,  H01L33/0062 ,  H01L33/0095 ,  H01L33/30

Abstract: A nanorod light emitting device, a method of manufacturing the same, and a display apparatus including the nanorod light emitting device are provided. The nanorod light emitting device includes a first semiconductor layer doped with a first conductivity type, a light emitting layer disposed on the first semiconductor layer, and a second semiconductor layer disposed on the light emitting layer and doped with a second conductivity type that is electrically opposite to the first conductivity type, wherein a distance between a lower surface of the first semiconductor layer and an upper surface of the second semiconductor layer is in a range of about 2 μm to about 10 μm, wherein a difference between a diameter of the upper surface of the second semiconductor layer and the lower surface of the first semiconductor layer is 10% or less of a diameter of the upper surface of the second semiconductor layer.