公开(公告)号：US20240361941A1

公开(公告)日：2024-10-31

申请号：US18307885

申请日：2023-04-27

申请人： Dell Products L.P.

发明人： Santoshkumar Konnur ,  Deepak Vokaliga ,  Ananthakrishnan Anirudhan ,  Shruti Asmita

IPC分类号： G06F3/06

CPC分类号： G06F3/0647 ,  G06F3/0613 ,  G06F3/0644 ,  G06F3/067

摘要： An example methodology includes, by a computing device, receiving a request to migrate a logical unit number (LUN) from a source array to a target array and, responsive to a determination that the LUN is a large LUN, dividing the large LUN into a plurality of partitions, creating a number of sessions corresponding to the plurality of partitions, wherein each session of the created sessions is operable to migrate data from a partition of the plurality of partitions, and initiating the created sessions to start copying data from the respective partitions in parallel. The method may also include, by the computing device, responsive to a determination that the LUN is not a large LUN, creating a single session operable to migrate data from the LUN and initiating the single session to start copying data from the LUN.

公开(公告)号：US20240361913A1

公开(公告)日：2024-10-31

申请号：US18642489

申请日：2024-04-22

申请人： Hiroaki Kohge ,  Hiroomi Motohashi

发明人： Hiroaki Kohge ,  Hiroomi Motohashi

IPC分类号： G06F3/06

CPC分类号： G06F3/0613 ,  G06F3/0656 ,  G06F3/0659 ,  G06F3/0676

摘要： An information processing apparatus includes a nonvolatile memory and circuitry. The nonvolatile memory stores data written using singled magnetic recording, in which tracks are partially arranged one over another in a radial direction. The circuitry is to instruct the nonvolatile memory to write the data in units of sectors, additionally write the data to a data writing area of the nonvolatile memory, create, on a volatile memory, a buffer for delayed writing in which the data to be written to the data writing area is temporarily held, and write the data in the buffer for delayed writing to the nonvolatile memory in a case that a total amount of data accumulated in the buffer for delayed writing exceeds a threshold value.

公开(公告)号：US20240329846A1

公开(公告)日：2024-10-03

申请号：US18129390

申请日：2023-03-31

申请人： Advanced Micro Devices, Inc.

发明人： Vignesh Adhinarayanan ,  Michael Ignatowski ,  Hyung-Dong Lee

IPC分类号： G06F3/06

CPC分类号： G06F3/0613 ,  G06F3/0634 ,  G06F3/0673

摘要： A memory sprint controller, responsive to an indicator of an irregular memory access phase, causes a memory controller to enter a sprint mode in which it temporarily adjusts at least one timing parameter of a dynamic random access memory (DRAM) to reduce a time in which a designated number of activate (ACT) commands are allowed to be dispatched to the DRAM.

公开(公告)号：US20240319885A1

公开(公告)日：2024-09-26

申请号：US18677326

申请日：2024-05-29

申请人： Hewlett Packard Enterprise Development LP

发明人： Mayukh Dutta ,  Aesha Dhar Roy ,  Manoj Srivatsav ,  Ganesha Devadiga ,  Geethanjali N. Rao ,  Prasenjit Saha ,  Jharna Aggarwal

IPC分类号： G06F3/06 ,  G06N20/00

CPC分类号： G06F3/0613 ,  G06F3/0659 ,  G06F3/067 ,  G06N20/00

摘要： In some examples, a system creates a training data set based on features of sample workloads, the training data set comprising labels associated with the features of the sample workloads, where the labels are based on load indicators generated in a computing environment relating to load conditions of the computing environment resulting from execution of the sample workloads. The system groups selected workloads into a plurality of workload clusters based on features of the selected workloads, and computes, using a model trained based on the training data set, parameters representing contributions of respective workload clusters of the plurality of workload clusters to a load in the computing environment. The system performs workload management in the computing environment based on the computed parameters.

公开(公告)号：US20240319884A1

公开(公告)日：2024-09-26

申请号：US18620773

申请日：2024-03-28

申请人： Micron Technology, Inc.

发明人： Hua Tan ,  Lingye Zhou

IPC分类号： G06F3/06

CPC分类号： G06F3/0613 ,  G06F3/0656 ,  G06F3/0673

摘要： Methods, systems, and devices for two-stage buffer operations supporting write commands are described. If data is written to a memory device starting at a multi-plane page offset other than zero, the read performance for the data may decrease significantly due to die misalignment. To avoid die misalignment, a memory system may support two buffers for write data: a flush buffer and a temporary buffer. The memory system may determine whether to add received data to the flush buffer, the temporary buffer, or a combination thereof based on a data transfer size and a threshold size. If the data in the temporary buffer satisfies a copy condition, the data in the temporary buffer is copied into the flush buffer. If the data in the flush buffer satisfies a flush condition, the data in the flush buffer is written to the memory device starting at a multi-plane page offset of zero.

公开(公告)号：US20240311054A1

公开(公告)日：2024-09-19

申请号：US18595769

申请日：2024-03-05

申请人： Samsung Electronics Co., Ltd.

发明人： Eun Chu OH ,  Beomkyu SHIN

IPC分类号： G06F3/06

CPC分类号： G06F3/0659 ,  G06F3/0613 ,  G06F3/064 ,  G06F3/0652 ,  G06F3/0673

摘要： Provided is a memory device including a plurality of memory blocks including of at least one subblock, wherein the memory block includes a first subblock configured to store first data including of at least one bit, and a second subblock configured to perform an erase operation independently of the first subblock and store second data including of at least one bit. The memory device is configured to perform a read operation on the second data in response to a write operation being performed on the second data in the second subblock. The memory device is configured to perform a write operation on the first data in the first subblock in response to a read operation being performed on the second data in the second subblock.

公开(公告)号：US12086418B1

公开(公告)日：2024-09-10

申请号：US18129436

申请日：2023-03-31

申请人： Advanced Micro Devices, Inc.

发明人： Vignesh Adhinarayanan ,  Michael Ignatowski ,  Hyung-Dong Lee

IPC分类号： G06F3/06

CPC分类号： G06F3/0613 ,  G06F3/0634 ,  G06F3/0673

摘要： A memory sprint controller, responsive to an indicator of an irregular memory access phase, causes a memory controller to enter a sprint mode in which it temporarily adjusts at least one timing parameter of a dynamic random access memory (DRAM) to reduce a time in which a designated number of activate (ACT) commands are allowed to be dispatched to the DRAM.

公开(公告)号：US12086417B2

公开(公告)日：2024-09-10

申请号：US18101281

申请日：2023-01-25

申请人： Dell Products L.P.

发明人： Amitai Alkalay ,  Vladimir Shveidel ,  Lior Kamran

IPC分类号： G06F3/06

CPC分类号： G06F3/0613 ,  G06F3/0647 ,  G06F3/067

摘要： Techniques can include: configuring a federation to have a volume as active from only a first storage system so that hosts only sends I/O operations, directed to the first volume, to the first storage system; configuring a second storage system of the federation as inactive with respect to volume; determining, in accordance with criteria, to allow I/O operations directed to the volume to be sent to both the first and second storage systems; transitioning the second storage system, with respect to the volume, from inactive to active; and receiving, from a host at the first and second storage systems, I/O operations directed to the volume while the first and second storage systems are configured as active. The I/O operations can include a first I/O operation received at the second storage system which is redirected, by the second storage system, to the first storage system for servicing.

公开(公告)号：US12086416B2

公开(公告)日：2024-09-10

申请号：US18058183

申请日：2022-11-22

申请人： SK hynix Inc.

发明人： Seon Ju Lee ,  Jeong Sun Park

IPC分类号： G06F3/06

CPC分类号： G06F3/0613 ,  G06F3/0659 ,  G06F3/0679

摘要： A memory system may wait to receive one or more read commands from a reference time point, and read data, requested by the one or more read commands, from the memory device in response to a determination that it is possible to simultaneously read data divided and stored, as an M number of data units, in an M number of planes among a plurality of planes in response to the one or more read commands or that a maximum read wait time has elapsed from the reference time point, M being a natural number.

公开(公告)号：US12086415B2

公开(公告)日：2024-09-10

申请号：US17662187

申请日：2022-05-05

申请人： Micron Technology, Inc.

发明人： Bryan David Kerstetter ,  Donald Martin Morgan

IPC分类号： G06F3/06

CPC分类号： G06F3/0613 ,  G06F3/0619 ,  G06F3/0659 ,  G06F3/0679

摘要： Methods, systems, and devices for frequency regulation for memory management commands are described. A memory device may maintain a respective first counter and second counter for each monitoring area of the memory device, where the counters may be incremented for each activate command received for the corresponding monitoring area. If the first counter satisfies a first threshold, an activate command issued to the monitoring area may be ignored. If the second counter fails to satisfy a second threshold, a memory management command issued to the monitoring area may be ignored and the memory device may maintain a value of the second counter, while decrementing the first counter. Alternatively, if the second counter satisfies the second threshold, the memory device may perform a memory management operation associated with a received memory management command and may decrement the first counter and the second counter.