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公开(公告)号：US20220156185A1
公开(公告)日：2022-05-19
申请号：US16952813
申请日：2020-11-19
发明人： Nicola Colella , Antonino Pollio , Hua Tan
IPC分类号： G06F12/0802 , G06F12/02
摘要： Methods, systems, and devices for read operations for regions of a memory device are described. In some examples, a memory device may include a first cache for storing mappings between logical addresses and physical addresses of the memory device, and a second cache for storing indices associated with entries removed from the first cache. The memory device may include a controller configured to load mappings to the first cache upon receiving read commands. When the first cache is full, and when the memory device receives a read command, the controller may remove an entry from the first cache and may store an index associated with the removed entry to the second cache. The controller may then transmit a mapping associated with the index to a host device for use in a HPB operation.
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公开(公告)号：US20240126685A1
公开(公告)日：2024-04-18
申请号：US17414299
申请日：2021-04-27
发明人： Hua Tan , Junjun Wang , De Hua Guo
IPC分类号： G06F12/02
CPC分类号： G06F12/0246
摘要： Methods, systems, and devices for dynamic voltage supply for memory circuit are described. An apparatus may adjust a supply voltage based on a process corner and a temperature of the memory system. An apparatus may include a memory array and a controller. The controller may determine a first temperature of the apparatus is less than a first temperature threshold at a first time. The controller may transition a voltage supplied to the controller from a first voltage level to a second voltage level based on determining the first temperature is less than the first temperature threshold. The controller may determine a second temperature is greater than a second temperature threshold at a second time. The controller may transition the voltage supplied to the controller from the second voltage level to the first voltage level based on determining the second temperature is greater than the second temperature threshold.
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公开(公告)号：US11886266B2
公开(公告)日：2024-01-30
申请号：US17736886
申请日：2022-05-04
发明人： Junjun Wang , Yanming Liu , Deping He , Hua Tan
IPC分类号： G06F1/00 , G06F1/3225 , G06F1/3296 , G06F3/06 , G06F1/3203
CPC分类号： G06F1/3225 , G06F1/3296 , G06F3/0625 , G06F3/0659 , G06F1/3203 , G06F3/0679
摘要： Methods, systems, and devices for dynamic power control are described. In some examples, a memory device may be configured to adjust a first duration for transitioning power modes. For example, the memory device may be configured to operate in a first power mode, a second power mode, and a third power mode. When operating in a second power mode, the memory device may be configured to increase or decrease the first duration for transitioning to a third power mode based on a second duration between received commands. If no commands are received during the first duration, the memory device may transition from the second power mode to the third power mode.
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公开(公告)号：US11670375B2
公开(公告)日：2023-06-06
申请号：US17458211
申请日：2021-08-26
发明人： Hua Tan , Jingxun Eric Wu , Yingying Zhu , Hui Yang , Bo Zhou
CPC分类号： G11C16/10 , G06F3/0604 , G06F3/0659 , G06F3/0679 , G11C16/0483 , G11C16/06 , G11C16/26 , G11C29/10 , G11C29/50
摘要： A memory device provides a memory array including memory cells, a temperature sensing circuit, and a memory control unit operatively coupled to the memory array. The memory control unit includes a processor. The processor is configured to receive temperature information from the temperature sensing circuit, initiate programming of the memory cells with data using a first threshold voltage distribution when the temperature information indicates an operating temperature is in a first temperature range, and initiate programming of the memory cells with data using a second threshold voltage distribution when the temperature information indicates the operating temperature is in a second temperature range.
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公开(公告)号：US11107533B2
公开(公告)日：2021-08-31
申请号：US16484881
申请日：2018-12-28
发明人： Hua Tan , Jingxun Eric Wu , Yingying Zhu , Hui Yang , Bo Zhou
摘要： A memory array including memory cells, a temperature sensing circuit, and a memory control unit operatively coupled to the memory array. The memory control unit includes a processor. The processor is configured to receive temperature information from the temperature sensing circuit, initiate programming of the memory cells with data using a first threshold voltage distribution when the temperature information indicates an operating temperature is in a first temperature range, and initiate programming of the memory cells with data using a second threshold voltage distribution when the temperature information indicates the operating temperature is in a second temperature range.
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公开(公告)号：US11886341B2
公开(公告)日：2024-01-30
申请号：US17850584
申请日：2022-06-27
发明人： Nicola Colella , Antonino Pollio , Hua Tan
IPC分类号： G06F12/00 , G06F12/0802 , G06F12/02
CPC分类号： G06F12/0802 , G06F12/0223 , G06F2212/604 , G06F2212/608
摘要： Methods, systems, and devices for read operations for regions of a memory device are described. In some examples, a memory device may include a first cache for storing mappings between logical addresses and physical addresses of the memory device, and a second cache for storing indices associated with entries removed from the first cache. The memory device may include a controller configured to load mappings to the first cache upon receiving read commands. When the first cache is full, and when the memory device receives a read command, the controller may remove an entry from the first cache and may store an index associated with the removed entry to the second cache. The controller may then transmit a mapping associated with the index to a host device for use in a HPB operation.
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公开(公告)号：US20230143181A1
公开(公告)日：2023-05-11
申请号：US16968371
申请日：2019-08-27
发明人： Hua Tan , Hui Yang , Mauro Luigi Sali
IPC分类号： G06F3/06 , G06F12/0815 , G06F12/02
CPC分类号： G06F3/0619 , G06F3/0656 , G06F3/0679 , G06F12/0815 , G06F12/0253 , G06F2212/1016
摘要： Upon receipt of a synchronize cache command, valid host data size in the SRAM write buffer is checked. If the valid data size is greater than a predetermined value, valid host data in the SRAM write buffer is flushed directly into an open MLC block based on a one-pass transfer program. However, if the valid host data size is less than the predetermined value, the host data is not flushed to an open MLC block but is instead flushed into a temporary storage location to satisfy the command specifications for a command to synchronize a cache. The host data is maintained in the SRAM write buffer, which receives additional data until full. Once full, the host data in the SRAM write buffer is transferred to an open MLC block in one-pass. If the host data in the write buffer is lost, it may be recovered from the temporary storage location.
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公开(公告)号：US20220397953A1
公开(公告)日：2022-12-15
申请号：US17736886
申请日：2022-05-04
发明人： Junjun Wang , Yanming Liu , Deping He , Hua Tan
IPC分类号： G06F1/3225 , G06F1/3296 , G06F3/06
摘要： Methods, systems, and devices for dynamic power control are described. In some examples, a memory device may be configured to adjust a first duration for transitioning power modes. For example, the memory device may be configured to operate in a first power mode, a second power mode, and a third power mode. When operating in a second power mode, the memory device may be configured to increase or decrease the first duration for transitioning to a third power mode based on a second duration between received commands. If no commands are received during the first duration, the memory device may transition from the second power mode to the third power mode.
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公开(公告)号：US20240319884A1
公开(公告)日：2024-09-26
申请号：US18620773
申请日：2024-03-28
发明人： Hua Tan , Lingye Zhou
IPC分类号： G06F3/06
CPC分类号： G06F3/0613 , G06F3/0656 , G06F3/0673
摘要： Methods, systems, and devices for two-stage buffer operations supporting write commands are described. If data is written to a memory device starting at a multi-plane page offset other than zero, the read performance for the data may decrease significantly due to die misalignment. To avoid die misalignment, a memory system may support two buffers for write data: a flush buffer and a temporary buffer. The memory system may determine whether to add received data to the flush buffer, the temporary buffer, or a combination thereof based on a data transfer size and a threshold size. If the data in the temporary buffer satisfies a copy condition, the data in the temporary buffer is copied into the flush buffer. If the data in the flush buffer satisfies a flush condition, the data in the flush buffer is written to the memory device starting at a multi-plane page offset of zero.
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公开(公告)号：US11972109B2
公开(公告)日：2024-04-30
申请号：US17283495
申请日：2021-03-01
发明人： Hua Tan , Lingye Zhou
IPC分类号： G06F3/06
CPC分类号： G06F3/0613 , G06F3/0656 , G06F3/0673
摘要： Methods, systems, and devices for two-stage buffer operations supporting write commands are described. If data is written to a memory device starting at a multi-plane page offset other than zero, the read performance for the data may decrease significantly due to die misalignment. To avoid die misalignment, a memory system may support two buffers for write data: a flush buffer and a temporary buffer. The memory system may determine whether to add received data to the flush buffer, the temporary buffer, or a combination thereof based on a data transfer size and a threshold size. If the data in the temporary buffer satisfies a copy condition, the data in the temporary buffer is copied into the flush buffer. If the data in the flush buffer satisfies a flush condition, the data in the flush buffer is written to the memory device starting at a multi-plane page offset of zero.
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