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公开(公告)号：US20240168669A1
公开(公告)日：2024-05-23
申请号：US18239576
申请日：2023-08-29
发明人： Eun Chu OH , Beomkyu SHIN
IPC分类号： G06F3/06
CPC分类号： G06F3/064 , G06F3/0604 , G06F3/0652 , G06F3/0679
摘要： A non-volatile memory device is provided. The non-volatile memory device includes: sub-blocks provided on a substrate. The sub-blocks include: a first sub-block connected to a first word line group including a first number of word lines; and a second sub-block connected to a second word line group including a second number of word lines. The first sub-block includes: at least one first memory cell storing M-bit data; and second memory cells each storing N-bit data. The second sub-block includes: at least one third memory cell storing K-bit data; and fourth memory cells each storing L-bit data. M, N, K, and L are positive integers, N is greater than M, and L is greater than K. The first number and the second number are different, and the at least one first memory cell and the at least one third memory cell include different numbers of memory cells.
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公开(公告)号：US20240069789A1
公开(公告)日：2024-02-29
申请号：US18136041
申请日：2023-04-18
发明人： Eun Chu OH , Beomkyu SHIN
CPC分类号： G06F3/0655 , G06F3/0604 , G06F3/0679 , G06F12/0253
摘要： The present disclosure provides storage devices and methods for operating the same. In some embodiments, a storage device includes a non-volatile memory including a plurality of sub-blocks that are independently erasable, and a processor configured to control a garbage collection operation on the plurality of sub-blocks. The plurality of sub-blocks includes a plurality of first sub-blocks that have a first block size and a plurality of second sub-blocks that have a second block size. The second block size is different from the first block size. The processor is further configured to select a victim sub-block with a lowest ratio of a valid page count to an invalid page count from among the plurality of sub-blocks, and copy a valid page of the victim sub-block to a target sub-block from among the plurality of sub-blocks.
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公开(公告)号：US20240311054A1
公开(公告)日：2024-09-19
申请号：US18595769
申请日：2024-03-05
发明人： Eun Chu OH , Beomkyu SHIN
IPC分类号： G06F3/06
CPC分类号： G06F3/0659 , G06F3/0613 , G06F3/064 , G06F3/0652 , G06F3/0673
摘要： Provided is a memory device including a plurality of memory blocks including of at least one subblock, wherein the memory block includes a first subblock configured to store first data including of at least one bit, and a second subblock configured to perform an erase operation independently of the first subblock and store second data including of at least one bit. The memory device is configured to perform a read operation on the second data in response to a write operation being performed on the second data in the second subblock. The memory device is configured to perform a write operation on the first data in the first subblock in response to a read operation being performed on the second data in the second subblock.
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公开(公告)号：US20230395111A1
公开(公告)日：2023-12-07
申请号：US18235189
申请日：2023-08-17
发明人： Kuiyon MUN , Beomkyu SHIN , Jaeyong JEONG
CPC分类号： G11C8/18 , G11C8/06 , G11C7/222 , G11C7/1066 , G11C7/1093 , G11C7/106 , G11C7/1087
摘要： A non-volatile memory device is provided. The non-volatile memory device includes a clock pin, a clock signal being received from a controller through the clock pin; a first input/output pin; a second input/output pin, data being received from the controller in synchronization with the clock signal through the second input/output pin; a command/address buffer configured to operate at a first operating speed and buffer a command and an address received through the first input/output pin in synchronization with the clock signal; a memory cell array including a plurality of memory cells; and a control logic configured to control operations with respect to the plurality of memory cells, based on the command and the address buffered in the command/address buffer.
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公开(公告)号：US20220101900A1
公开(公告)日：2022-03-31
申请号：US17549095
申请日：2021-12-13
发明人： Kuiyon MUN , Beomkyu SHIN , Jaeyong JEONG
摘要： A non-volatile memory device is provided. The non-volatile memory device includes a clock pin, a clock signal being received from a controller through the clock pin; a first input/output pin; a second input/output pin, data being received from the controller in synchronization with the clock signal through the second input/output pin; a command/address buffer configured to operate at a first operating speed and buffer a command and an address received through the first input/output pin in synchronization with the clock signal; a memory cell array including a plurality of memory cells; and a control logic configured to control operations with respect to the plurality of memory cells, based on the command and the address buffered in the command/address buffer.
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