On-die receiver coupling capacitance testing

    公开(公告)号:US10862714B1

    公开(公告)日:2020-12-08

    申请号:US16670175

    申请日:2019-10-31

    Applicant: XILINX, INC.

    Abstract: A method for testing on-die capacitors is provided. The method comprises transmitting, during a first time period, a first modulated testing signal from a first transmitter port of a transmitter to a first receiver port of a receiver along a first path of a differential signal, the first receiver port connected to a first on-die capacitor in the receiver along the first path; driving, during the first time period, a constant voltage on a second transmitter port of the transmitter to a second receiver port of the receiver along a second path of the differential signal comprising a second on-die capacitor; and determining whether the first on-die capacitor is functional, based on the first modulated testing signal.

    Clock phase aligner for high speed data serializers

    公开(公告)号:US10712770B1

    公开(公告)日:2020-07-14

    申请号:US16042785

    申请日:2018-07-23

    Applicant: Xilinx, Inc.

    Abstract: Apparatus and associated methods relate to a high-speed data serializer with a clock calibration module including a main multiplexer (MMUX), a replicated multiplexer (RMUX), a duty cycle calibration module (DCC), and a set of adjustable delay lines (ADLs), the ADLs generating calibrated clocks from a set of system clocks, the DCC sensing duty cycle and phase of the calibrated clocks. In an illustrative example, the DCC may generate error signals indicative of deviation from an expected duty cycle using low-pass filters. The error signals control the ADLs, which may provide continuous corrections to the calibrated clocks, for example. The MMUX and RMUX may receive the calibrated clocks, the RMUX generating a duty cycle indicating clock-to-data phasing, the MMUX providing live data multiplexing, for example. Various multiplexer calibration schemes may reduce jitter, which may facilitate increased data rates associated with high-speed serial data streams.

    Thermal calibration of a ring modulator

    公开(公告)号:US10651933B1

    公开(公告)日:2020-05-12

    申请号:US16421425

    申请日:2019-05-23

    Applicant: Xilinx, Inc.

    Abstract: Systems and methods for calibrating a ring modulator are described. A system may include a controller configured to provide a first test signal to the ring modulator, determine a first candidate temperature control signal for a heater of the ring modulator when the first test signal is provided to the ring modulator, determine a first optical swing of an optical signal at a drop port of the ring modulator, determine a second candidate temperature control signal for the heater when the first test signal is provided to the ring modulator, determine a second optical swing of an optical signal at the drop port, select an optimal optical swing from the first optical swing and the second optical swing, and select one of the first candidate temperature control signal or the second candidate temperature control signal based on the optimal optical swing selected.

    Fast transient low drop-out voltage regulator for a voltage-mode driver

    公开(公告)号:US09746864B1

    公开(公告)日:2017-08-29

    申请号:US15234584

    申请日:2016-08-11

    Applicant: Xilinx, Inc.

    CPC classification number: G05F1/56 H03F3/3064 H03F3/45192 H04B1/04 H04B1/16

    Abstract: An example voltage regulator includes an output transistor that includes a source coupled to a first voltage supply node and a drain coupled to an output node. The voltage regulator further includes a first transistor that includes a source coupled to the output node, and a second transistor that includes a source coupled to a gate of the output transistor and a drain coupled to a second voltage supply node. The voltage regulator further includes a resistor coupled between the second voltage supply node and a first node that includes the drain of the first transistor and a gate of the second transistor. The voltage regulator further includes an error amplifier that includes a first input coupled to a reference voltage node, a second input coupled to the output node, and an output coupled to a gate of the first transistor.

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