公开(公告)号：US11314277B1

公开(公告)日：2022-04-26

申请号：US16532293

申请日：2019-08-05

Applicant: XILINX, INC.

Inventor： Riyas Noorudeen Remla ,  Gourav Modi ,  Azarudin Abdulla ,  Chee Chong Chan

IPC: G06F1/00 ,  G06F1/10 ,  G06F13/42 ,  G06F9/54 ,  G06F9/30 ,  G06F30/34

Abstract: Examples described herein provide a method for reducing lane-to-lane serial skew in an integrated circuit. In an example using a processor-based system, a maximum clock skew is determined from clock skews of respective lanes of a transmitter of the IC. Each of the clock skews corresponds to a skew of a clock signal of the respective lane relative to a same reference clock signal. A skew match amount is determined for each lane of the lanes of the transmitter. The skew match amount for a respective lane of the lanes is based on the maximum clock skew and the clock skew of the respective lane. Configuration data is generated to configure the transmitter to shift incoming data for each lane of the lanes based on the skew match amount for the respective lane.

公开(公告)号：US10924096B1

公开(公告)日：2021-02-16

申请号：US16808053

申请日：2020-03-03

Applicant: Xilinx, Inc.

Inventor： Gourav Modi ,  Chee Chong Chan ,  Azarudin Abdulla ,  Riyas Noorudeen Remla

IPC: H03K5/135 ,  H05K1/02 ,  G06F1/10 ,  H03K5/00

Abstract: Apparatus and associated methods relate to a dynamic lane-to-lane skew reduction technique having (a) a clocking architecture configured to provide a corresponding first delayed clock signal and a corresponding second delayed clock signal through a first and a second plurality of routing traces, respectively, and (b) a number of skew compensation circuits configured to process the corresponding first delayed clock signal and the corresponding second delayed clock signal to generate a corresponding user clock signal for a corresponding lane of a transmitter. In an illustrative example, a first routing trace may transmit a first delayed clock signal in a direction opposite to a second routing trace transmitting a second delayed clock signal. By implementing the technique, each transmitter lane may receive a corresponding user clock signal having substantially the same delay relative to a reference clock signal such that dynamic lane-to-lane skew may be advantageously reduced.

公开(公告)号：US11695535B2

公开(公告)日：2023-07-04

申请号：US17199193

申请日：2021-03-11

Applicant: XILINX, INC.

Inventor： John Edward McGrath ,  Gourav Modi ,  Rhona Wade

IPC: H04L5/14 ,  H03D7/00 ,  H03K19/177

CPC classification number: H04L5/14 ,  H03D7/00 ,  H03K19/177

Abstract: Embodiments herein describe an integrated circuit with a digital front end (DFE) that includes multiple hardened mixers that can be configured to support multiple different radio paths. The DFE provides the ability to distribute the processing across the multiple mixers, which can be combined and synchronized to create a larger mixer or may be used in other combinations to create multiple discrete mixers.

公开(公告)号：US10651933B1

公开(公告)日：2020-05-12

申请号：US16421425

申请日：2019-05-23

Applicant: Xilinx, Inc.

Inventor： Ping-Chuan Chiang ,  Kee Hian Tan ,  Gourav Modi ,  Nakul Narang ,  Haibing Zhao ,  Yohan Frans

IPC: H04B10/079 ,  G02F1/025 ,  G02F1/015

Abstract: Systems and methods for calibrating a ring modulator are described. A system may include a controller configured to provide a first test signal to the ring modulator, determine a first candidate temperature control signal for a heater of the ring modulator when the first test signal is provided to the ring modulator, determine a first optical swing of an optical signal at a drop port of the ring modulator, determine a second candidate temperature control signal for the heater when the first test signal is provided to the ring modulator, determine a second optical swing of an optical signal at the drop port, select an optimal optical swing from the first optical swing and the second optical swing, and select one of the first candidate temperature control signal or the second candidate temperature control signal based on the optimal optical swing selected.