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公开(公告)号：US20240331603A1
公开(公告)日：2024-10-03
申请号：US18740677
申请日：2024-06-12
Inventor： Mingyue LI , Chao TIAN , Yanqing GUAN , Fei AI , Guanghui LIU
IPC: G09G3/20
CPC classification number: G09G3/20 , G09G2310/0267 , G09G2310/0283
Abstract: The present application discloses a gate drive circuit and a display device. The gate drive circuit includes a plurality of cascaded gate drive units, in which one of the gate drive units includes a first layout, an input module and a pull-up module. By receiving a potential changeable signal by the gate of a first transistor or the gate of a second thin-film transistor, it can alleviate or avoid current leakage caused when a first node keeps at a same voltage level for a long time, thereby improving the stability of the potential of the first node.
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公开(公告)号：US20230274701A1
公开(公告)日：2023-08-31
申请号：US17622633
申请日：2021-12-15
Inventor： Chao TIAN , Yanqing GUAN , Guanghui LIU , Fei AI
IPC: G09G3/3266 , G09G3/36 , G06F3/041
CPC classification number: G09G3/3266 , G09G3/3674 , G06F3/0412 , G06F3/04166 , G06F3/0418 , G09G2310/08 , G09G2354/00
Abstract: A gate driving circuit and a display device are provided. The gate driving circuit includes electrically connected multi-stage driving units. The driving unit of each stage includes an input module, an output module electrically connected with the input module, a pull-down module electrically connected with the output module, and a pull-down control module electrically connected with the pull-down module. The output module is electrically connected to a stage transmission signal output terminal, and the pull-down module is electrically connected to a first control signal terminal.
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公开(公告)号：US20220189429A1
公开(公告)日：2022-06-16
申请号：US17261014
申请日：2020-06-30
Inventor： Chao TIAN
IPC: G09G3/36
Abstract: A gate driver on array (GOA) circuit, a display panel and a display device are provided. The GOA circuit includes m cascaded GOA units. An nth-stage GOA unit includes a second feedback module. The second feedback module, electrically connected to the second node of the nth-stage GOA unit, a first node of the (n−1)th-stage GOA unit, the clock signal of the (n+1)th-stage GOA unit, a gate driving signal of the nth-stage GOA unit and the constant low voltage signal, to pull down voltage applied on a second node of the nth-stage GOA unit. The one-way feedback could achieve the linear design more easily, raise the circuit stability, and thus the GOA circuit could be integrated in the display panel more easily to achieve the design of placing the GOA circuit in the active area.
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公开(公告)号：US20210408072A1
公开(公告)日：2021-12-30
申请号：US16769254
申请日：2020-02-28
Inventor： Juncheng XIAO , Chao TIAN , Yanqing GUAN , Haiming CAO
Abstract: A display panel, a gate electrode driving circuit, and an electronic device are provided. The display panel includes a first metal layer including a first gate electrode; a second metal layer including a first source electrode, a first drain electrode, and a second gate electrode; two ends of a polycrystalline silicon semiconductor layer electrically connected to the first source electrode and the first drain electrode respectively; a third metal layer including a second source electrode and a second drain electrode; and two ends of a metal oxide semiconductor layer electrically connected to the second source electrode and the second drain electrode respectively.
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公开(公告)号：US20190333944A1
公开(公告)日：2019-10-31
申请号：US16086019
申请日：2018-08-07
Inventor： Juncheng XIAO , Chao TIAN
IPC: H01L27/12 , H01L29/786 , H01L29/66
Abstract: The present disclosure provides an LTPS type TFT and a method for manufacturing the same. The TFT includes a first contact hole and a second contact hole, where the first contact hole and the second contact hole pass through the third insulating layer, the second insulating layer, and a portion of the first insulating layer, such that a portion of the heavily doped area is exposed. In addition, a transparent electrode is electrically connected to the source/drain electrode or the second gate electrode and a portion of the heavily doped area.
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Patent Agency Ranking
公开(公告)号：US20250098307A1
公开(公告)日：2025-03-20
申请号：US18567221
申请日：2023-09-26
Inventor： Haiming CAO , Chao TIAN , Shiyu LONG , Chunpeng ZHANG , Fei AI , Chungching HSIEH , Jianfeng YUAN
IPC: H01L27/12 , G02F1/1368 , H01L29/786
Abstract: An array substrate, a display panel, and a display device are provided. The array substrate includes a base; a buffer layer and a thin film transistor. The buffer layer is provided on the base and includes a first buffer layer and a second buffer layer. The first buffer layer is disposed between the second buffer layer and the base. A refractive index of the first buffer layer is greater than a refractive index of the base and a refractive index of the second buffer layer. A ratio of the refractive index of the first buffer layer to the refractive index of the base is less than or equal to 1.25. The thin film transistor is provided on a side of the buffer layer away from the base.
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公开(公告)号：US20250087124A1
公开(公告)日：2025-03-13
申请号：US18249250
申请日：2023-02-28
Inventor： Mingyue LI , Chao TIAN , Fei AI
Abstract: The present application discloses a display panel, the display panel includes an active area and a irregular-shaped area, the active area includes a first active area disposed at at least one side of the irregular-shaped area and a second active area connected with the first active area. The first signal line is disposed in the second active area, the second signal line is disposed in the first active area, the first signal line and the second signal line extend in a same direction, and the length of the first signal line is larger than the length of the second signal line, and at least one of a plurality of the compensation units is connected with the second signal line.
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公开(公告)号：US20240297174A1
公开(公告)日：2024-09-05
申请号：US17293332
申请日：2021-03-31
Inventor： Xuebin YUAN , Yanqing GUAN , Congxing YANG , Chao TIAN , Fuhsiung TANG
IPC: H01L27/12
CPC classification number: H01L27/124
Abstract: The present application provides an array substrate, a display panel, and a display device. In the present application, a plurality of first-type data lines and a plurality of second-type data lines with data voltages of opposite polarities are provided, and a light-shielding layer of each of first sub-pixels is at least electrically connected to a light-shielding layer of one of second sub-pixels through a connecting line, which can effectively reduce a change in pixel brightness caused by capacitive coupling, and relieve a problem of image flicker.
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公开(公告)号：US20240055535A1
公开(公告)日：2024-02-15
申请号：US17598275
申请日：2021-08-06
Inventor： Hong CHENG , Chao TIAN , Yanqing GUAN , Guanghui LIU
IPC: H01L29/786 , H01L29/423
CPC classification number: H01L29/78696 , H01L29/42384 , G02F1/1368
Abstract: A thin film transistor and a display panel are provided. A first dimension of a first transmission portion electrically connected to a source heavily-doped portion is different from a second dimension of a second transmission portion electrically connected to a drain heavily-doped portion, so that an intensity of an electric field of carriers transmitted by the transmission portion corresponding to the larger one of the first dimension or the second dimension is smaller when the thin film transistor is turned on, thereby reducing the bombardment effect of the carriers on a source or a drain and improving the stability of thin film transistor.
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公开(公告)号：US20240029609A1
公开(公告)日：2024-01-25
申请号：US17441303
申请日：2021-08-06
Inventor： Haiming CAO , Chao TIAN , Yanqing GUAN , Fei AI , Guanghui LIU
IPC: G09G3/20
CPC classification number: G09G3/20 , G09G2310/0267 , G09G2310/08 , G09G2320/045
Abstract: A gate drive circuit and a display panel are provided. A pull-up module and a pull-down module of the gate drive circuit output a constant-voltage high potential to a second node, a third node, and a n-th stage gate drive signal through a P-type thin film transistor and output constant-voltage low potential through a N-type thin film transistor to the second node, the third node, and an n-th gate drive signal, thereby improving the stability of the output signal of the thin film transistor connected to the gate drive circuit and the key node.
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