公开(公告)号：US20220165844A1

公开(公告)日：2022-05-26

申请号：US17670528

申请日：2022-02-14

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Cheng-Pu Chiu ,  Tzung-Ying Lee ,  Dien-Yang Lu ,  Chun-Kai Chao ,  Chun-Mao Chiou

IPC: H01L29/06 ,  H01L29/78

Abstract: A semiconductor device includes a substrate having a logic region and a high-voltage (HV) region, a first gate structure on the HV region, a first epitaxial layer and a second epitaxial layer adjacent to one side of the first gate structure, a first contact plug between the first epitaxial layer and the second epitaxial layer, a third epitaxial layer and a fourth epitaxial layer adjacent to another side of the first gate structure, and a second contact plug between the third epitaxial layer and the fourth epitaxial layer. Preferably, a bottom surface of the first epitaxial layer is lower than a bottom surface of the first contact plug and a bottom surface of the third epitaxial layer is lower than a bottom surface of the second contact plug.

公开(公告)号：US11764261B2

公开(公告)日：2023-09-19

申请号：US17670528

申请日：2022-02-14

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Cheng-Pu Chiu ,  Tzung-Ying Lee ,  Dien-Yang Lu ,  Chun-Kai Chao ,  Chun-Mao Chiou

IPC: H01L29/06 ,  H01L29/78

CPC classification number: H01L29/0649 ,  H01L29/7851

Abstract: A semiconductor device includes a substrate having a logic region and a high-voltage (HV) region, a first gate structure on the HV region, a first epitaxial layer and a second epitaxial layer adjacent to one side of the first gate structure, a first contact plug between the first epitaxial layer and the second epitaxial layer, a third epitaxial layer and a fourth epitaxial layer adjacent to another side of the first gate structure, and a second contact plug between the third epitaxial layer and the fourth epitaxial layer. Preferably, a bottom surface of the first epitaxial layer is lower than a bottom surface of the first contact plug and a bottom surface of the third epitaxial layer is lower than a bottom surface of the second contact plug.

公开(公告)号：US11289572B1

公开(公告)日：2022-03-29

申请号：US17100963

申请日：2020-11-23

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Cheng-Pu Chiu ,  Tzung-Ying Lee ,  Dien-Yang Lu ,  Chun-Kai Chao ,  Chun-Mao Chiou

IPC: H01L29/66 ,  H01L21/8238 ,  H01L29/165 ,  H01L29/45 ,  H01L21/02 ,  H01L27/092 ,  H01L29/08 ,  H01L29/06 ,  H01L29/78

Abstract: A semiconductor device includes a substrate having a logic region and a high-voltage (HV) region, a first gate structure on the HV region, a first epitaxial layer and a second epitaxial layer adjacent to one side of the first gate structure, a first contact plug between the first epitaxial layer and the second epitaxial layer, a third epitaxial layer and a fourth epitaxial layer adjacent to another side of the first gate structure, and a second contact plug between the third epitaxial layer and the fourth epitaxial layer. Preferably, a bottom surface of the first epitaxial layer is lower than a bottom surface of the first contact plug and a bottom surface of the third epitaxial layer is lower than a bottom surface of the second contact plug.

公开(公告)号：US10366896B2

公开(公告)日：2019-07-30

申请号：US15688852

申请日：2017-08-28

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： I-Fan Chang ,  Yen-Liang Wu ,  Wen-Tsung Chang ,  Jui-Ming Yang ,  Jie-Ning Yang ,  Chi-Ju Lee ,  Chun-Ting Chiang ,  Bo-Yu Su ,  Chih-Wei Lin ,  Dien-Yang Lu

IPC: H01L21/28 ,  H01L29/423 ,  H01L29/66

Abstract: A method for fabricating semiconductor device includes the steps of first forming a gate dielectric layer on a substrate; forming a gate material layer on the gate dielectric layer, and removing part of the gate material layer and part of the gate dielectric layer to form a gate electrode, in which a top surface of the gate dielectric layer adjacent to two sides of the gate electrode is lower than a top surface of the gate dielectric layer between the gate electrode and the substrate. Next, a first mask layer is formed on the gate dielectric layer and the gate electrode, part of the first mask layer and part of the gate dielectric layer are removed to form a first spacer, a second mask layer is formed on the substrate and the gate electrode, and part of the second mask layer is removed to form a second spacer.

公开(公告)号：US20250040198A1

公开(公告)日：2025-01-30

申请号：US18917997

申请日：2024-10-16

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Cheng-Pu Chiu ,  Tzung-Ying Lee ,  Dien-Yang Lu ,  Chun-Kai Chao ,  Chun-Mao Chiou

IPC: H01L29/06 ,  H01L29/78

Abstract: A semiconductor device includes a substrate having a logic region and a high-voltage (HV) region, a first gate structure on the HV region, a first epitaxial layer and a second epitaxial layer adjacent to one side of the first gate structure, a first fin-shaped structure between the first epitaxial layer and the substrate, and a first contact plug between the first epitaxial layer and the second epitaxial layer. Preferably, the first gate structure includes a gate dielectric layer, top surfaces of the gate dielectric layer and the first fin-shaped structure are coplanar, and a bottom surface of the first epitaxial layer is lower than a bottom surface of the first contact plug.

公开(公告)号：US20230395657A1

公开(公告)日：2023-12-07

申请号：US18235358

申请日：2023-08-18

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Cheng-Pu Chiu ,  Tzung-Ying Lee ,  Dien-Yang Lu ,  Chun-Kai Chao ,  Chun-Mao Chiou

IPC: H01L29/06 ,  H01L29/78

CPC classification number: H01L29/0649 ,  H01L29/7851

Abstract: A semiconductor device includes a substrate having a logic region and a high-voltage (HV) region, a first gate structure on the HV region, a first epitaxial layer and a second epitaxial layer adjacent to one side of the first gate structure, a first contact plug between the first epitaxial layer and the second epitaxial layer, a third epitaxial layer and a fourth epitaxial layer adjacent to another side of the first gate structure, and a second contact plug between the third epitaxial layer and the fourth epitaxial layer. Preferably, a bottom surface of the first epitaxial layer is lower than a bottom surface of the first contact plug and a bottom surface of the third epitaxial layer is lower than a bottom surface of the second contact plug.

公开(公告)号：US20190043725A1

公开(公告)日：2019-02-07

申请号：US15688852

申请日：2017-08-28

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： I-Fan Chang ,  Yen-Liang Wu ,  Wen-Tsung Chang ,  Jui-Ming Yang ,  Jie-Ning Yang ,  Chi-Ju Lee ,  Chun-Ting Chiang ,  Bo-Yu Su ,  Chih-Wei Lin ,  Dien-Yang Lu

IPC: H01L21/28 ,  H01L29/66 ,  H01L29/423

CPC classification number: H01L21/28167 ,  H01L29/42368 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/6656

Abstract: A method for fabricating semiconductor device includes the steps of first forming a gate dielectric layer on a substrate; forming a gate material layer on the gate dielectric layer, and removing part of the gate material layer and part of the gate dielectric layer to form a gate electrode, in which a top surface of the gate dielectric layer adjacent to two sides of the gate electrode is lower than a top surface of the gate dielectric layer between the gate electrode and the substrate. Next, a first mask layer is formed on the gate dielectric layer and the gate electrode, part of the first mask layer and part of the gate dielectric layer are removed to form a first spacer, a second mask layer is formed on the substrate and the gate electrode, and part of the second mask layer is removed to form a second spacer.

公开(公告)号：US12148796B2

公开(公告)日：2024-11-19

申请号：US18235358

申请日：2023-08-18

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Cheng-Pu Chiu ,  Tzung-Ying Lee ,  Dien-Yang Lu ,  Chun-Kai Chao ,  Chun-Mao Chiou

IPC: H01L29/06 ,  H01L29/78

Abstract: A semiconductor device includes a substrate having a logic region and a high-voltage (HV) region, a first gate structure on the HV region, a first epitaxial layer and a second epitaxial layer adjacent to one side of the first gate structure, a first contact plug between the first epitaxial layer and the second epitaxial layer, a third epitaxial layer and a fourth epitaxial layer adjacent to another side of the first gate structure, and a second contact plug between the third epitaxial layer and the fourth epitaxial layer. Preferably, a bottom surface of the first epitaxial layer is lower than a bottom surface of the first contact plug and a bottom surface of the third epitaxial layer is lower than a bottom surface of the second contact plug.

公开(公告)号：US20230411213A1

公开(公告)日：2023-12-21

申请号：US17868786

申请日：2022-07-20

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Wen-Wen Zhang ,  Ming-Chou Lu ,  Kun-Chen Ho ,  Dien-Yang Lu ,  Chun-Lung Chen ,  Chung-Yi Chiu

IPC: H01L21/768 ,  H01L23/528 ,  H01L21/311 ,  H01L29/66

CPC classification number: H01L21/76897 ,  H01L21/76832 ,  H01L21/7682 ,  H01L23/528 ,  H01L21/31116 ,  H01L29/66545

Abstract: A method for fabricating a semiconductor device includes the steps of forming a gate structure on a substrate, forming a contact etch stop layer (CESL) on the gate structure, forming an interlayer dielectric (ILD) layer on the CESL, forming a contact plug in the ILD layer and adjacent to the gate structure, forming a first stop layer on the ILD layer, and removing the first stop layer and the ILD layer around the gate structure to form an air gap exposing the CESL.

公开(公告)号：US11239082B2

公开(公告)日：2022-02-01

申请号：US16438416

申请日：2019-06-11

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： I-Fan Chang ,  Yen-Liang Wu ,  Wen-Tsung Chang ,  Jui-Ming Yang ,  Jie-Ning Yang ,  Chi-Ju Lee ,  Chun-Ting Chiang ,  Bo-Yu Su ,  Chih-Wei Lin ,  Dien-Yang Lu

IPC: H01L21/28 ,  H01L29/423 ,  H01L29/66 ,  H01L29/51

Abstract: A method for fabricating semiconductor device includes the steps of first forming a gate dielectric layer on a substrate; forming a gate material layer on the gate dielectric layer, and removing part of the gate material layer and part of the gate dielectric layer to form a gate electrode, in which a top surface of the gate dielectric layer adjacent to two sides of the gate electrode is lower than a top surface of the gate dielectric layer between the gate electrode and the substrate. Next, a first mask layer is formed on the gate dielectric layer and the gate electrode, part of the first mask layer and part of the gate dielectric layer are removed to form a first spacer, a second mask layer is formed on the substrate and the gate electrode, and part of the second mask layer is removed to forma second spacer.