公开(公告)号：US20220165844A1

公开(公告)日：2022-05-26

申请号：US17670528

申请日：2022-02-14

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Cheng-Pu Chiu ,  Tzung-Ying Lee ,  Dien-Yang Lu ,  Chun-Kai Chao ,  Chun-Mao Chiou

IPC: H01L29/06 ,  H01L29/78

Abstract: A semiconductor device includes a substrate having a logic region and a high-voltage (HV) region, a first gate structure on the HV region, a first epitaxial layer and a second epitaxial layer adjacent to one side of the first gate structure, a first contact plug between the first epitaxial layer and the second epitaxial layer, a third epitaxial layer and a fourth epitaxial layer adjacent to another side of the first gate structure, and a second contact plug between the third epitaxial layer and the fourth epitaxial layer. Preferably, a bottom surface of the first epitaxial layer is lower than a bottom surface of the first contact plug and a bottom surface of the third epitaxial layer is lower than a bottom surface of the second contact plug.

公开(公告)号：US20250040198A1

公开(公告)日：2025-01-30

申请号：US18917997

申请日：2024-10-16

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Cheng-Pu Chiu ,  Tzung-Ying Lee ,  Dien-Yang Lu ,  Chun-Kai Chao ,  Chun-Mao Chiou

IPC: H01L29/06 ,  H01L29/78

Abstract: A semiconductor device includes a substrate having a logic region and a high-voltage (HV) region, a first gate structure on the HV region, a first epitaxial layer and a second epitaxial layer adjacent to one side of the first gate structure, a first fin-shaped structure between the first epitaxial layer and the substrate, and a first contact plug between the first epitaxial layer and the second epitaxial layer. Preferably, the first gate structure includes a gate dielectric layer, top surfaces of the gate dielectric layer and the first fin-shaped structure are coplanar, and a bottom surface of the first epitaxial layer is lower than a bottom surface of the first contact plug.

公开(公告)号：US20230395657A1

公开(公告)日：2023-12-07

申请号：US18235358

申请日：2023-08-18

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Cheng-Pu Chiu ,  Tzung-Ying Lee ,  Dien-Yang Lu ,  Chun-Kai Chao ,  Chun-Mao Chiou

IPC: H01L29/06 ,  H01L29/78

CPC classification number: H01L29/0649 ,  H01L29/7851

Abstract: A semiconductor device includes a substrate having a logic region and a high-voltage (HV) region, a first gate structure on the HV region, a first epitaxial layer and a second epitaxial layer adjacent to one side of the first gate structure, a first contact plug between the first epitaxial layer and the second epitaxial layer, a third epitaxial layer and a fourth epitaxial layer adjacent to another side of the first gate structure, and a second contact plug between the third epitaxial layer and the fourth epitaxial layer. Preferably, a bottom surface of the first epitaxial layer is lower than a bottom surface of the first contact plug and a bottom surface of the third epitaxial layer is lower than a bottom surface of the second contact plug.

公开(公告)号：US11764261B2

公开(公告)日：2023-09-19

申请号：US17670528

申请日：2022-02-14

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Cheng-Pu Chiu ,  Tzung-Ying Lee ,  Dien-Yang Lu ,  Chun-Kai Chao ,  Chun-Mao Chiou

IPC: H01L29/06 ,  H01L29/78

CPC classification number: H01L29/0649 ,  H01L29/7851

Abstract: A semiconductor device includes a substrate having a logic region and a high-voltage (HV) region, a first gate structure on the HV region, a first epitaxial layer and a second epitaxial layer adjacent to one side of the first gate structure, a first contact plug between the first epitaxial layer and the second epitaxial layer, a third epitaxial layer and a fourth epitaxial layer adjacent to another side of the first gate structure, and a second contact plug between the third epitaxial layer and the fourth epitaxial layer. Preferably, a bottom surface of the first epitaxial layer is lower than a bottom surface of the first contact plug and a bottom surface of the third epitaxial layer is lower than a bottom surface of the second contact plug.

公开(公告)号：US11289572B1

公开(公告)日：2022-03-29

申请号：US17100963

申请日：2020-11-23

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Cheng-Pu Chiu ,  Tzung-Ying Lee ,  Dien-Yang Lu ,  Chun-Kai Chao ,  Chun-Mao Chiou

IPC: H01L29/66 ,  H01L21/8238 ,  H01L29/165 ,  H01L29/45 ,  H01L21/02 ,  H01L27/092 ,  H01L29/08 ,  H01L29/06 ,  H01L29/78

Abstract: A semiconductor device includes a substrate having a logic region and a high-voltage (HV) region, a first gate structure on the HV region, a first epitaxial layer and a second epitaxial layer adjacent to one side of the first gate structure, a first contact plug between the first epitaxial layer and the second epitaxial layer, a third epitaxial layer and a fourth epitaxial layer adjacent to another side of the first gate structure, and a second contact plug between the third epitaxial layer and the fourth epitaxial layer. Preferably, a bottom surface of the first epitaxial layer is lower than a bottom surface of the first contact plug and a bottom surface of the third epitaxial layer is lower than a bottom surface of the second contact plug.

公开(公告)号：US09130032B2

公开(公告)日：2015-09-08

申请号：US14465579

申请日：2014-08-21

Applicant: United Microelectronics Corp.

Inventor： Hsin-Fu Huang ,  Kun-Hsien Lin ,  Chi-Mao Hsu ,  Min-Chuan Tsai ,  Tzung-Ying Lee ,  Chin-Fu Lin

IPC: H01L29/78 ,  H01L21/28 ,  H01L29/49 ,  H01L29/66 ,  H01L29/51

CPC classification number: H01L29/78 ,  H01L21/28088 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66545

Abstract: Provided is a semiconductor device including a substrate, a gate structure, a second dielectric layer and a source/drain region. A first dielectric layer is disposed on the substrate, and the first dielectric layer has a trench therein. The gate structure is disposed on the substrate in the trench and includes a work function metal layer and a metal layer. The work function metal layer is disposed in the trench, and includes a TiAl3 phase metal layer. A height of the work function metal layer disposed on a sidewall of the trench is lower than a height of a top surface of the first dielectric layer. The metal layer fills the trench. The second dielectric layer is disposed between the gate structure and the substrate. The source/drain region is disposed in the substrate at two sides of the gate structure.

Abstract translation: 提供了一种包括基板，栅极结构，第二介电层和源极/漏极区域的半导体器件。 第一电介质层设置在基板上，并且第一介电层在其中具有沟槽。 栅极结构设置在沟槽中的衬底上，并且包括功函数金属层和金属层。 工作功能金属层设置在沟槽中，并且包括TiAl 3相金属层。 布置在沟槽的侧壁上的功函数金属层的高度低于第一电介质层的顶表面的高度。 金属层填充沟槽。 第二电介质层设置在栅极结构和衬底之间。 源极/漏极区域在栅极结构的两侧设置在衬底中。

公开(公告)号：US12148796B2

公开(公告)日：2024-11-19

申请号：US18235358

申请日：2023-08-18

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Cheng-Pu Chiu ,  Tzung-Ying Lee ,  Dien-Yang Lu ,  Chun-Kai Chao ,  Chun-Mao Chiou

IPC: H01L29/06 ,  H01L29/78

Abstract: A semiconductor device includes a substrate having a logic region and a high-voltage (HV) region, a first gate structure on the HV region, a first epitaxial layer and a second epitaxial layer adjacent to one side of the first gate structure, a first contact plug between the first epitaxial layer and the second epitaxial layer, a third epitaxial layer and a fourth epitaxial layer adjacent to another side of the first gate structure, and a second contact plug between the third epitaxial layer and the fourth epitaxial layer. Preferably, a bottom surface of the first epitaxial layer is lower than a bottom surface of the first contact plug and a bottom surface of the third epitaxial layer is lower than a bottom surface of the second contact plug.

公开(公告)号：US20140361386A1

公开(公告)日：2014-12-11

申请号：US14465579

申请日：2014-08-21

Applicant: United Microelectronics Corp.

Inventor： Hsin-Fu Huang ,  Kun-Hsien Lin ,  Chi-Mao Hsu ,  Min-Chuan Tsai ,  Tzung-Ying Lee ,  Chin-Fu Lin

IPC: H01L29/78 ,  H01L29/49

CPC classification number: H01L29/78 ,  H01L21/28088 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66545

Abstract: Provided is a semiconductor device including a substrate, a gate structure, a second dielectric layer and a source/drain region. A first dielectric layer is disposed on the substrate, and the first dielectric layer has a trench therein. The gate structure is disposed on the substrate in the trench and includes a work function metal layer and a metal layer. The work function metal layer is disposed in the trench, and includes a TiAl3 phase metal layer. A height of the work function metal layer disposed on a sidewall of the trench is lower than a height of a top surface of the first dielectric layer. The metal layer fills the trench. The second dielectric layer is disposed between the gate structure and the substrate. The source/drain region is disposed in the substrate at two sides of the gate structure.

Abstract translation: 提供了一种包括基板，栅极结构，第二介电层和源极/漏极区域的半导体器件。 第一电介质层设置在基板上，并且第一介电层在其中具有沟槽。 栅极结构设置在沟槽中的衬底上，并且包括功函数金属层和金属层。 工作功能金属层设置在沟槽中，并且包括TiAl 3相金属层。 布置在沟槽的侧壁上的功函数金属层的高度低于第一电介质层的顶表面的高度。 金属层填充沟槽。 第二电介质层设置在栅极结构和衬底之间。 源极/漏极区域在栅极结构的两侧设置在衬底中。