-
公开(公告)号：US10707213B2
公开(公告)日：2020-07-07
申请号：US16178521
申请日：2018-11-01
Inventor： Chia-Hung Wang , En-Chiuan Liou , Chien-Hao Chen , Sho-Shen Lee , Yi-Ting Chen , Jhao-Hao Lee
IPC: H01L21/311 , H01L27/108 , H01L21/027 , H01L21/033
Abstract: A method of forming a layout of a semiconductor device includes the following steps. First line patterns extend along a first direction in a first area and a second area, but the first line patterns extend along a second direction in a boundary area. Second line patterns extend along a third direction in the first area and the second area, but the second line patterns extend along a fourth direction in the boundary area, so that minimum distances between overlapping areas of the first line patterns and the second line patterns in the boundary area are larger than minimum distances between overlapping areas of the first line patterns and the second line patterns in the first area and the second area. A trimming process is performed to shade the first line patterns and the second line patterns in the boundary area and the second area.
-
公开(公告)号：US20170139329A1
公开(公告)日：2017-05-18
申请号：US14940108
申请日：2015-11-12
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： En-Chiuan Liou , Chia-Hung Wang
CPC classification number: G03F7/70141 , G01B11/272 , G03F7/70633
Abstract: A semiconductor processing method is provided and includes the following steps. A first semiconductor process is performed for a wafer to obtain plural overlay datum (x, y), wherein x and y are respectively shift values in X-direction and Y-direction. Next, A re-correct process is performed by a computer, wherein the re-correct process comprises: (a) providing an overlay tolerance value (A, B) and an original out of specification value (OOS %), wherein A and B are respectively predetermined tolerance values in X-direction and Y-direction; (b) providing at least a k value (kx, ky); (c) modifying the overlay datum (x, y) according to the k value (kx, ky) to obtain at least a revised overlay datum (x′, y′) ; and (d) calculating a process parameter from the revised overlay datum (x′, y′). Lastly, a second semiconductor process is performed according to the process parameter . . . . The present invention further provides a lithography system.
-
公开(公告)号：US10692785B2
公开(公告)日：2020-06-23
申请号：US16057826
申请日：2018-08-08
Inventor： Chien-Hao Chen , Chien-Wei Huang , Chia-Hung Wang , Sho-Shen Lee
Abstract: A semiconductor pattern for monitoring overlay and critical dimension at post-etching stage is provided in the present invention, which include a first inverted-T shaped pattern with a base portion and a middle portion extending from the base portion and a second pattern adjacent and spaced apart from the base portion of the first inverted-T shaped pattern, wherein the first inverted-T shaped pattern and the second pattern are composed of a plurality of spacer patterns spaced apart from each other.
-
公开(公告)号：US20200111791A1
公开(公告)日：2020-04-09
申请号：US16178521
申请日：2018-11-01
Inventor： Chia-Hung Wang , En-Chiuan Liou , Chien-Hao Chen , Sho-Shen Lee , Yi-Ting Chen , Jhao-Hao Lee
IPC: H01L27/108 , H01L21/033 , H01L21/027 , H01L21/311
Abstract: A method of forming a layout of a semiconductor device includes the following steps. First line patterns extend along a first direction in a first area and a second area, but the first line patterns extend along a second direction in a boundary area. Second line patterns extend along a third direction in the first area and the second area, but the second line patterns extend along a fourth direction in the boundary area, so that minimum distances between overlapping areas of the first line patterns and the second line patterns in the boundary area are larger than minimum distances between overlapping areas of the first line patterns and the second line patterns in the first area and the second area. A trimming process is performed to shade the first line patterns and the second line patterns in the boundary area and the second area.
-
公开(公告)号：US10535610B2
公开(公告)日：2020-01-14
申请号：US16003090
申请日：2018-06-07
Inventor： Feng-Yi Chang , Fu-Che Lee , Yi-Wang Zhan , Chia-Liang Liao , Yu-Cheng Tung , Chien-Hao Chen , Chia-Hung Wang
IPC: H01L23/544 , H01L27/108 , H01L21/311
Abstract: A semiconductor structure is disclosed. The semiconductor structure includes a substrate having a scribe line region. A material layer is formed on the scribe line region and has a rectangular region defined therein. The rectangular region has a pair of first edges parallel with a widthwise direction of the scribe line region and a pair of second edges parallel with a lengthwise direction of the scribe line region. A pair of first alignment features is formed in the material layer along the first edges, and a pair of second alignment features is formed in the material layer along the second edges. The space between the pair of first alignment features is larger than a space between the pair of the second alignment features.
-
Patent Agency Ranking
6.发明申请公开(公告)号：US20180374765A1
公开(公告)日：2018-12-27
申请号：US16057826
申请日：2018-08-08
Inventor： Chien-Hao Chen , Chien-Wei Huang , Chia-Hung Wang , Sho-Shen Lee
IPC: H01L21/66
Abstract: A semiconductor pattern for monitoring overlay and critical dimension at post-etching stage is provided in the present invention, which include a first inverted-T shaped pattern with a base portion and a middle portion extending from the base portion and a second pattern adjacent and spaced apart from the base portion of the first inverted-T shaped pattern, wherein the first inverted-T shaped pattern and the second pattern are composed of a plurality of spacer patterns spaced apart from each other.
-
公开(公告)号：US09964866B2
公开(公告)日：2018-05-08
申请号：US15065872
申请日：2016-03-10
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Che-Yi Lin , En-Chiuan Liou , Chia-Hsun Tseng , Yi-Ting Chen , Chia-Hung Wang , Yi-Jing Wang
CPC classification number: G03F9/7003
Abstract: A method of forming an integrated circuit includes the following steps. A substrate including a plurality of exposure fields is provided, and each of the exposure field includes a target portion and a set of alignment marks. Measure the set of alignment marks of each exposure field by a measuring system to obtain alignment data for the respective exposure field. Determine an exposure parameter corresponding to each exposure field and an exposure location on the target portion from the alignment data for the respective exposure field by a calculating system. Feedback the alignment data to a next substrate.
-
公开(公告)号：US20170220728A1
公开(公告)日：2017-08-03
申请号：US15065872
申请日：2016-03-10
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Che-Yi Lin , En-Chiuan Liou , Chia-Hsun Tseng , Yi-Ting Chen , Chia-Hung Wang , Yi-Jing Wang
CPC classification number: G03F9/7003
Abstract: A method of forming an integrated circuit includes the following steps. A substrate including a plurality of exposure fields is provided, and each of the exposure field includes a target portion and a set of alignment marks. Measure the set of alignment marks of each exposure field by a measuring system to obtain alignment data for the respective exposure field. Determine an exposure parameter corresponding to each exposure field and an exposure location on the target portion from the alignment data for the respective exposure field by a calculating system. Feedback the alignment data to a next substrate.
-
公开(公告)号：US20160307850A1
公开(公告)日：2016-10-20
申请号：US14687912
申请日：2015-04-15
Applicant: United Microelectronics Corp.
Inventor： Chia-Ching Lin , En-Chiuan Liou , Chia-Hung Wang , Sho-Shen Lee
IPC: H01L23/544 , H01L29/78
CPC classification number: H01L29/785 , G03F7/70633 , G03F7/70683
Abstract: An overlay mark for determining the alignment between two separately generated patterns formed along with two successive layers above a substrate is provided in the present invention, wherein both the substrate and the overlay mark include at least two pattern zones having periodic structures with different orientations, and the periodic structures of the overlay mark are orthogonally overlapped with the periodic structures of the substrate.
Abstract translation: 在本发明中提供了用于确定在衬底上方与两个连续层形成的两个单独产生的图案之间的对准的覆盖标记，其中衬底和覆盖标记都包括具有不同取向的周期性结构的至少两个图案区域，以及 覆盖标记的周期性结构与衬底的周期性结构正交地重叠。
-
公开(公告)号：US09400435B2
公开(公告)日：2016-07-26
申请号：US14457136
申请日：2014-08-12
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： En-Chiuan Liou , Chia-Chang Hsu , Teng-Chin Kuo , Chia-Hung Wang , Tuan-Yen Yu , Yuan-Chi Pai , Chun-Chi Yu
CPC classification number: G03F7/70633 , G03F1/42 , G03F7/70491 , G05B19/188 , G05B2219/45027 , G05B2219/45031
Abstract: A method of correcting an overlay error includes the following steps. First, an overlay mark disposed on a substrate is captured so as to generate overlay mark information. The overlay mark includes at least a pair of first mark patterns and at least a second mark pattern above the first mark patterns. Then, the overlay mark information is calculated to generate an offset value between two first mark patterns and to generate a shift value between the second mark pattern and one of the first mark patterns. Finally, the offset value is used to compensate the shift value so as to generate an amended shift value.
Abstract translation: 校正重叠错误的方法包括以下步骤。 首先，捕获设置在基板上的覆盖标记，以生成重叠标记信息。 覆盖标记包括至少一对第一标记图案和至少第一标记图案上方的第二标记图案。 然后，计算叠加标记信息以产生两个第一标记图案之间的偏移值，并产生第二标记图案与第一标记图案之一之间的偏移值。 最后，偏移值用于补偿偏移值，以产生修正的移位值。
-
-
-
-
-
-
-
-
-
Search Results
16
records
(took 0.014 seconds)
