Invention Grant
- Patent Title: Semiconductor pattern for monitoring overlay and critical dimension at post-etching stage and metrology method of the same
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Application No.: US16057826Application Date: 2018-08-08
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Publication No.: US10692785B2Publication Date: 2020-06-23
- Inventor: Chien-Hao Chen , Chien-Wei Huang , Chia-Hung Wang , Sho-Shen Lee
- Applicant: UNITED MICROELECTRONICS CORP. , Fujian Jinhua Integrated Circuit Co., Ltd.
- Applicant Address: TW Hsin-Chu CN Quanzhou, Fujian Province
- Assignee: UNITED MICROELECTRONICS CORP.,Fujian Jinhua Integrated Circuit Co., Ltd.
- Current Assignee: UNITED MICROELECTRONICS CORP.,Fujian Jinhua Integrated Circuit Co., Ltd.
- Current Assignee Address: TW Hsin-Chu CN Quanzhou, Fujian Province
- Agent Winston Hsu
- Main IPC: H01L23/58
- IPC: H01L23/58 ; H01L29/10 ; H01L21/66
Abstract:
A semiconductor pattern for monitoring overlay and critical dimension at post-etching stage is provided in the present invention, which include a first inverted-T shaped pattern with a base portion and a middle portion extending from the base portion and a second pattern adjacent and spaced apart from the base portion of the first inverted-T shaped pattern, wherein the first inverted-T shaped pattern and the second pattern are composed of a plurality of spacer patterns spaced apart from each other.
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Information query
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