公开(公告)号：US4963862A

公开(公告)日：1990-10-16

申请号：US216915

申请日：1988-07-08

Applicant: Takeo Nakabayashi ,  Hirohisa Machida

Inventor： Takeo Nakabayashi ,  Hirohisa Machida

IPC: H04J3/24 ,  H04L12/24 ,  H04Q3/52 ,  H04Q3/74 ,  H04Q11/04

CPC classification number: H04L41/00 ,  H04J3/24 ,  H04L12/24 ,  H04Q11/0471 ,  H04Q3/523 ,  H04Q3/74 ,  H04Q2213/042 ,  H04Q2213/097 ,  H04Q2213/103 ,  H04Q2213/13103 ,  H04Q2213/13209 ,  H04Q2213/13216 ,  H04Q2213/13299 ,  H04Q2213/13305 ,  H04Q2213/1332 ,  H04Q2213/204 ,  H04Q2213/32

Abstract: This invention relates to a terminal identifier control circuit which provides automatic start of the check procedure to examine the unassigned/assigned distinction of a limited number of terminal identifiers by hardware, in a communications apparatus with a number of terminal equipment connected to a network.

Abstract translation: 终端标识符控制电路本发明涉及一种终端标识符控制电路，该终端标识符控制电路在具有与网络连接的多个终端设备的通信设备中提供自动启动检查程序以检查有限数量的终端标识符的未分配/分配的区别。

公开(公告)号：US5048010A

公开(公告)日：1991-09-10

申请号：US421872

申请日：1989-10-16

Applicant: Takeo Nakabayashi ,  Hirohisa Machida

Inventor： Takeo Nakabayashi ,  Hirohisa Machida

IPC: H04Q11/04

CPC classification number: H04Q11/0428

Abstract: A communication control processor for storing own data being set respectively for plural data links, and parameters related thereto or address of the other memory in which the parameters related to the data link are stored, in a CAM and address accessed by retrieval of the CAM, respectively. By retrieving the CAM according to the own data of the data link, the parameters related to the data link are to be read, updated, or cleared.

Abstract translation: 一种通信控制处理器，用于存储分别为多个数据链路设置的自己的数据，以及与其相关的参数或其中存储与数据链路有关的参数的另一个存储器的地址存储在通过CAM检索访问的CAM和地址中， 分别。 通过根据数据链路的自身数据检索CAM，与数据链路相关的参数将被读取，更新或清除。

公开(公告)号：US4943965A

公开(公告)日：1990-07-24

申请号：US217585

申请日：1988-07-11

Applicant: Hirohisa Machida ,  Takeo Nakabayashi

Inventor： Hirohisa Machida ,  Takeo Nakabayashi

IPC: H04L1/08 ,  G06F11/08 ,  H03M5/14 ,  H03M13/00 ,  H04L25/49

CPC classification number: G06F11/08 ,  H03M5/145 ,  H04L25/4906

Abstract: A digital signal decoding method and a circuit therefor which, when each data of first and second 1-bit of a set of 3-bit data received is a logical "1", decodes the data to 1-bit data of "1". When each of the data of the first and second 1-bit is "0", decodes the data to 1-bit data of "0". And when first and second 1-bit data is a combination of "1" and "0", directly decodes a third bit, thereby enabling a quick decoding result to be obtained when receiving the data.

Abstract translation: 一种数字信号解码方法及其电路，当接收到的一组3位数据的第一和第二1位的每个数据为逻辑“1”时，将数据解码为1位数据。 当第一个和第二个1位的每个数据为“0”时，将数据解码为1位数据“0”。 并且当第一和第二1比特数据是“1”和“0”的组合时，直接解码第三比特，从而使得能够在接收到数据时获得快速解码结果。

公开(公告)号：US4827157A

公开(公告)日：1989-05-02

申请号：US125470

申请日：1987-11-27

Applicant: Hirohisa Machida ,  Takeo Nakabayashi

Inventor： Hirohisa Machida ,  Takeo Nakabayashi

IPC: H03K3/037 ,  H03K5/151 ,  H03K3/356

CPC classification number: H03K5/1515

Abstract: In a periodic signal generator circuit, logical threshold values of an inverter for inverting an output signal of a first logical gate circuit (1) and inputting the same to a second logical gate circuit (2) and an inverter (40) for inverting an output signal of the second logical gate circuit (2) and inputting the same to the first logical gate circuit are set low, so that the time when an output signal of one of the logical gate circuits (1, 2) is inverted by inverting an output signal of the other logical gate circuit is delayed. Thus, the periodic signal generator circuit generates a so-called two-phase non-overlapped clock signal.

Abstract translation: 在周期性信号发生器电路中，用于将第一逻辑门电路（1）的输出信号反相并将其输入到第二逻辑门电路（2）的反相器的逻辑阈值和用于将输出 第二逻辑门电路（2）的信号并将其输入到第一逻辑门电路被设置为低，使得逻辑门电路（1,2）之一的输出信号通过将输出 另一逻辑门电路的信号被延迟。 因此，周期性信号发生器电路产生所谓的两相非重叠时钟信号。

公开(公告)号：US4811267A

公开(公告)日：1989-03-07

申请号：US162306

申请日：1988-02-29

Applicant: Hideki Ando ,  Harufusa Kondo ,  Hirohisa Machida

Inventor： Hideki Ando ,  Harufusa Kondo ,  Hirohisa Machida

IPC: G06F17/10 ,  G06F7/544 ,  G06F17/16 ,  G06F7/38

CPC classification number: G06F7/5443

Abstract: A digital signal processor includes a digital memory, a controller, an arithmetic operation unit and an interconnecting bus. The memory includes a shift register having an addressable output for storing values which are supplied to a multiplier circuit of the arithmetic operation unit. Use of the shift register provides a data delay minimizing the number of instructions required to implement delay processing. In the arithmetic operation unit, the output from the multiplier is connected to an arithmetic logic unit which, in turn, is connected to an accumulator. The accumulator temporarily stores data from the arithmetic logic unit and output the result onto the data bus. The operations of the signal process are directed by the controller which includes a program memory, an instruction register, and an instruction decoder.

Abstract translation: 数字信号处理器包括数字存储器，控制器，算术运算单元和互连总线。 存储器包括具有可寻址输出的移位寄存器，用于存储提供给算术运算单元的乘法器电路的值。 使用移位寄存器提供数据延迟，最小化实现延迟处理所需的指令数量。 在算术运算单元中，乘法器的输出连接到算术逻辑单元，算术逻辑单元又连接到累加器。 累加器临时存储来自算术逻辑单元的数据，并将结果输出到数据总线上。 信号处理的操作由包括程序存储器，指令寄存器和指令译码器的控制器引导。

公开(公告)号：US06442580B1

公开(公告)日：2002-08-27

申请号：US09357157

申请日：1999-07-19

Applicant: Hirohisa Machida

Inventor： Hirohisa Machida

IPC: G06F1717

CPC classification number: H03H17/0226 ,  G06F17/17 ,  H03H17/0282

Abstract: The resampler circuit according to the present invention is arranged such that the number of multiplication, that is, the number of multiplying means is reduced by storing the coefficients in each of the time intervals between the time point at which the time interval T has elapsed and a predetermined time point in a plurality of ROMs, taking advantage of the symmetrical characteristic of the waveform 1 indicated by the SINC function in the direction in which the number of T increments and that in which the number of −T increments, except the time intervals from the reference time 0, namely [0, T] and [0, −T]. In addition, the ROM size is also reduced by storing in each ROM the coefficients for only a half of each of the time intervals on the basis of the above symmetrical characteristic.

Abstract translation: 根据本发明的重采样电路被布置为通过在经过时间间隔T的时间点和时间间隔T经过的时间点之间的每个时间间隔中存储系数来减少乘法数，即乘法装置的数量， 在多个ROM中的预定时间点，利用由SINC功能指示的波形1的对称特性，其中T增量的数量和-T增加的方向除了时间间隔 从参考时间0，即[0，T]和[0，-T]。 此外，ROM尺寸也通过基于上述对称特性在每个ROM中仅存储每个时间间隔的一半的系数来减少。

公开(公告)号：US5426599A

公开(公告)日：1995-06-20

申请号：US63488

申请日：1993-05-19

Applicant: Hirohisa Machida

Inventor： Hirohisa Machida

IPC: G06F7/533 ,  G06F7/52 ,  G06F7/523 ,  G06F7/53

CPC classification number: G06F7/5336 ,  G06F7/5338

Abstract: The multiplier includes a register circuit for holding a multiplicand X, a multiplier register circuit for holding a multiplier Y, a second order Booth decoder circuit for decoding prescribed less significant bits of the multiplier Y according to the second Booth algorithm, and a third order Booth decode circuit for decoding more significant bits of the multiplier Y according to the third Booth algorithm. A tripled of the multiplicand X is produced in a 3X producing circuit in parallel with a multiplication operation utilizing the second Booth algorithm in an adder array. The output of adder array together with the output of 3X producing circuit is applied to an adder array for executing a multiplication operation according to the third order Booth algorithm. Production of an odd number multiple data of the multiplicand necessary for the third order Booth algorithm is executed in parallel with the multiplication operation according to the second order Booth algorithm, and therefore time required for producing the triple can apparently be eliminated. Thus, a multiplier capable of executing multiplication at a high speed in a hardware manner is provided.

Abstract translation: 乘法器包括用于保持被乘数X的寄存器电路，用于保持乘法器Y的乘法器寄存器电路，用于根据第二布斯算法对乘法器Y的规定的较低有效位进行解码的二阶布斯解码器电路，以及第三级布尔 解码电路，用于根据第三布斯算法对乘法器Y的更高有效位进行解码。 被乘数X的三倍产生在3X生成电路中，并且与利用加法器阵列中的第二布斯算法的乘法运算并行。 将加法器阵列的输出与3X产生电路的输出一起应用于根据三阶布斯算法执行乘法运算的加法器阵列。 与根据二阶布斯算法的乘法运算并行执行三阶布斯算法所需的被乘数的奇数多个数据的生成，因此可以明显地消除生成三元组所需的时间。 因此，提供能够以硬件方式高速执行乘法的乘法器。

公开(公告)号：US07956661B2

公开(公告)日：2011-06-07

申请号：US12362271

申请日：2009-01-29

Applicant: Hirohisa Machida

Inventor： Hirohisa Machida

IPC: H03K3/00

CPC classification number: H03K3/0375 ,  G01R31/318541

Abstract: The present invention provides a standard cell and a scan flip flop circuit capable of introducing a scan test also to a system LSI having an ACS circuit. One standard cell is configured by: a 3-input selection circuit for selecting one signal from three input signals; and a flip flop circuit. The 3-input selection circuit receives a control signal and a test signal at its control input part and its first input part, respectively. First and second signals are supplied to second and third input parts, and a selection signal is supplied to a selector input part. On the basis of the control signal and the selection signal, any of the signals input to the first to third input parts is output from the output part.

Abstract translation: 本发明提供了能够对具有ACS电路的系统LSI进行扫描测试的标准单元和扫描触发电路。 一个标准单元由三输入选择电路组成，用于从三个输入信号中选择一个信号; 和触发电路。 3输入选择电路在其控制输入部分及其第一输入部分分别接收控制信号和测试信号。 第一和第二信号被提供给第二和第三输入部分，并且选择信号被提供给选择器输入部分。 基于控制信号和选择信号，从输出部分输出输入到第一至第三输入部分的任何信号。

公开(公告)号：US06587504B1

公开(公告)日：2003-07-01

申请号：US09432176

申请日：1999-11-02

Applicant: Shuji Murakami ,  Hirohisa Machida ,  Hiroyuki Mizutani ,  Hiroshi Ochi

Inventor： Shuji Murakami ,  Hirohisa Machida ,  Hiroyuki Mizutani ,  Hiroshi Ochi

IPC: H03H730

CPC classification number: H04L25/03019 ,  H03H21/0012

Abstract: Following arrangement of an adaptive equalizer with a direct filter structure according to the least mean square error architecture, look ahead conversion of modifying a tap coefficient of the next cycle utilizing the tap coefficient of a predetermined preceding cycle is carried out and then a retiming process of adjusting the timing of tap coefficients and signals is carried out to arrange delay elements, whereby a transposition filter is realized. A high-speed adaptive equalizer is provided that can have the critical path reduced without increasing the hardware amount and that is superior in expansionability.

Abstract translation: 在根据最小均方误差结构配置具有直接滤波器结构的自适应均衡器之后，执行利用预定的前一周期的抽头系数修改下一周期的抽头系数的前瞻转换，然后进行重新定时处理 调整抽头系数和信号的定时进行排列延迟元件，从而实现置换滤波器。 提供了一种高速自适应均衡器，其可以在不增加硬件量的情况下降低关键路径，并且具有优异的可扩展性。

公开(公告)号：US5386528A

公开(公告)日：1995-01-31

申请号：US874921

申请日：1992-04-29

Applicant: Hideki Ando ,  Hirohisa Machida

Inventor： Hideki Ando ,  Hirohisa Machida

IPC: G06F7/02 ,  G06F12/10 ,  G06F12/12 ,  G11C15/00

CPC classification number: G11C15/00 ,  G06F12/123 ,  G06F7/02 ,  G06F12/1027

Abstract: An address translator has an improved data comparison circuit for comparing two pieces of data having n bits, e.g., 12 bits. In the data comparison circuit, cell circuits compare two pieces of data for every corresponding 4 bits. When a match is detected in the comparison of a set of 4 bits, a signal representative of the comparison result of the lower-order bits is bypassed. Hence, delay of signal propagation which may occur in the cell circuit in which the match is detected is reduced.

Abstract translation: 地址转换器具有改进的数据比较电路，用于比较具有n位的两个数据，例如12位。 在数据比较电路中，单元电路对每个相应的4位数据进行比较。 当在一组4比特的比较中检测到匹配时，旁路表示低位比特的比较结果的信号。 因此，可以在检测到匹配的单元电路中发生的信号传播的延迟减小。