公开(公告)号：US20190103493A1

公开(公告)日：2019-04-04

申请号：US16207081

申请日：2018-11-30

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Kuo-Chi TU ,  Jen-Sheng YANG ,  Sheng-Hung SHIH ,  Tong-Chern ONG ,  Wen-Ting CHU

IPC: H01L29/78 ,  H01L29/51 ,  H01L29/66 ,  G11C11/22 ,  H01L27/1159 ,  H01L27/11592

Abstract: A semiconductor device includes a memory circuit and a logic circuit. The memory circuit includes a word line, a bit line, a common line and a memory transistor having a gate coupled to the word line, a drain coupled to the bit line and a source coupled to the common line. The logic circuit includes a field effect transistor (FET) having a gate, a drain and a source. The memory transistor has a gate electrode layer formed on a gate dielectric layer, and the gate dielectric layer includes a first insulating layer and a first ferroelectric (FE) material layer. The FET has a gate electrode layer formed on a gate dielectric layer, and the gate dielectric layer includes a second insulating layer and a second FE material layer.

公开(公告)号：US20180151746A1

公开(公告)日：2018-05-31

申请号：US15640127

申请日：2017-06-30

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Kuo-Chi Tu ,  Jen-Sheng YANG ,  Sheng-Hung SHIH ,  Tong-Chern ONG ,  Wen-Ting CHU

IPC: H01L29/78 ,  H01L27/1159 ,  H01L27/11592 ,  H01L29/51 ,  H01L29/66 ,  G11C11/22

CPC classification number: H01L29/78391 ,  G11C11/223 ,  G11C11/2257 ,  G11C11/2273 ,  H01L27/1159 ,  H01L27/11592 ,  H01L29/513 ,  H01L29/516 ,  H01L29/66545 ,  H01L29/6684

Abstract: A semiconductor device includes a memory circuit and a logic circuit. The memory circuit includes a word line, a bit line, a common line and a memory transistor having a gate coupled to the word line, a drain coupled to the bit line and a source coupled to the common line. The logic circuit includes a field effect transistor (FET) having a gate, a drain and a source. The memory transistor has a gate electrode layer formed on a gate dielectric layer, and the gate dielectric layer includes a first insulating layer and a first ferroelectric (FE) material layer. The FET has a gate electrode layer formed on a gate dielectric layer, and the gate dielectric layer includes a second insulating layer and a second FE material layer.

公开(公告)号：US20190035458A1

公开(公告)日：2019-01-31

申请号：US15898119

申请日：2018-02-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Lien Linus LU ,  Yu-Der CHIH ,  Chung-Cheng CHOU ,  Tong-Chern ONG

IPC: G11C13/00 ,  G06F12/14

CPC classification number: G11C13/0038 ,  G06F12/1425 ,  G06F21/64 ,  G06F21/79 ,  G11C7/24 ,  G11C13/0004 ,  G11C13/0059 ,  G11C13/0069 ,  G11C2013/0083 ,  G11C2213/79

Abstract: A circuit includes a memory array having a plurality of memory cells; a control logic circuit, coupled to the memory array, and configured to use a first voltage signal to cause a first memory cell of the plurality of memory cells to transition from a first resistance state to a second resistance state, and a second voltage signal to cause the first memory cell to transition from the second resistance state to a third resistance state; and a counter circuit, coupled to the control logic circuit, and configured to increment a count by one in response to the first memory cell's transition from the first to the second resistance state, and again increment the count by one in response to the first memory cell's transition from the second to the third resistance state.

公开(公告)号：US20140256063A1

公开(公告)日：2014-09-11

申请号：US14280732

申请日：2014-05-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ping-Lin YANG ,  Jun-De JIN ,  Fu-Lung HSUEH ,  Sa-Lly LIU ,  Tong-Chern ONG ,  Chun-Jung LIN ,  Ya-Chen KAO

IPC: H01L25/065 ,  H01L23/522

CPC classification number: H01L25/0657 ,  H01F5/00 ,  H01F27/2804 ,  H01F41/046 ,  H01F2027/2809 ,  H01L23/48 ,  H01L23/5227 ,  H01L2225/06531 ,  H01L2924/0002 ,  Y10T29/4902 ,  H01L2924/00

Abstract: A communications structure comprises a first semiconductor substrate having a first coil, and a second semiconductor substrate having a second coil above the first semiconductor substrate. Inner edges of the first and second coils define a boundary of a volume that extends below the first coil and above the second coil. A ferromagnetic core is positioned at least partially within the boundary, such that a mutual inductance is provided between the first and second coils for wireless transmission of signals or power between the first and second coils.

Abstract translation: 通信结构包括具有第一线圈的第一半导体衬底和在第一半导体衬底上方具有第二线圈的第二半导体衬底。 第一和第二线圈的内边缘限定在第一线圈下方延伸并在第二线圈之上的体积的边界。 铁磁芯至少部分地位于边界内，使得在第一和第二线圈之间提供互感以在第一和第二线圈之间无线地传输信号或电力。