公开(公告)号：US20210057409A1

公开(公告)日：2021-02-25

申请号：US16794044

申请日：2020-02-18

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Harry-Hak-Lay CHUANG ,  Wei-Cheng WU ,  Ya-Chen KAO

IPC: H01L27/092 ,  H01L21/8238

Abstract: A semiconductor device includes active gate structures and dummy gate electrodes. The active gate structures are above an active region of a substrate. The dummy gate electrodes are above the active region of the substrate. A number of the dummy gate electrodes is less than a number of the active gate structures. The active gate structures and the dummy gate electrodes have different materials, and a distance between adjacent one of the dummy gate electrodes and one of the active gate structures is substantially the same as a gate pitch of the active gate structures.

公开(公告)号：US20180342529A1

公开(公告)日：2018-11-29

申请号：US16055357

申请日：2018-08-06

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Harry-Hak-Lay CHUANG ,  Wei-Cheng WU ,  Ya-Chen KAO

IPC: H01L27/11568 ,  H01L27/11573 ,  H01L29/66 ,  H01L29/423 ,  H01L21/8238 ,  H01L29/51

Abstract: A method for manufacturing a semiconductor device is provided. The method includes forming a split gate stack having a main gate and a select gate and forming a logic gate stack having a logic gate over a semiconductor substrate. The main gate and the logic gate is respectively replaced with a metal memory gate and a metal logic gate, in which the main gate and the logic gate are replaced simultaneously.

公开(公告)号：US20140256063A1

公开(公告)日：2014-09-11

申请号：US14280732

申请日：2014-05-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ping-Lin YANG ,  Jun-De JIN ,  Fu-Lung HSUEH ,  Sa-Lly LIU ,  Tong-Chern ONG ,  Chun-Jung LIN ,  Ya-Chen KAO

IPC: H01L25/065 ,  H01L23/522

CPC classification number: H01L25/0657 ,  H01F5/00 ,  H01F27/2804 ,  H01F41/046 ,  H01F2027/2809 ,  H01L23/48 ,  H01L23/5227 ,  H01L2225/06531 ,  H01L2924/0002 ,  Y10T29/4902 ,  H01L2924/00

Abstract: A communications structure comprises a first semiconductor substrate having a first coil, and a second semiconductor substrate having a second coil above the first semiconductor substrate. Inner edges of the first and second coils define a boundary of a volume that extends below the first coil and above the second coil. A ferromagnetic core is positioned at least partially within the boundary, such that a mutual inductance is provided between the first and second coils for wireless transmission of signals or power between the first and second coils.

Abstract translation: 通信结构包括具有第一线圈的第一半导体衬底和在第一半导体衬底上方具有第二线圈的第二半导体衬底。 第一和第二线圈的内边缘限定在第一线圈下方延伸并在第二线圈之上的体积的边界。 铁磁芯至少部分地位于边界内，使得在第一和第二线圈之间提供互感以在第一和第二线圈之间无线地传输信号或电力。

公开(公告)号：US20200279857A1

公开(公告)日：2020-09-03

申请号：US16875934

申请日：2020-05-15

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Harry-Hak-Lay CHUANG ,  Wei-Cheng WU ,  Ya-Chen KAO

IPC: H01L27/11568 ,  H01L29/66 ,  H01L27/11573

Abstract: A memory device includes a semiconductor substrate, a select gate stack, a main gate, a charge trapping layer, and a spacer. The a select gate stack is over the semiconductor substrate. The main gate is over the semiconductor substrate. The charge trapping layer has a first portion between the main gate and the semiconductor substrate. The spacer is on a sidewall of the main gate. At least a portion of the main gate is between the spacer and the select gate stack, and a lowermost surface of the spacer is above a lowermost surface of the main gate.

公开(公告)号：US20150129952A1

公开(公告)日：2015-05-14

申请号：US14075817

申请日：2013-11-08

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Harry Hak-Lay CHUANG ,  Wei-Cheng WU ,  Ya-Chen KAO

IPC: H01L27/115 ,  H01L29/78

CPC classification number: H01L27/11568 ,  H01L21/823842 ,  H01L27/11573 ,  H01L29/42368 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66545

Abstract: A semiconductor device includes a substrate, at least one split gate memory device, and at least one logic device. The split gate memory device is disposed on the substrate. The logic device is disposed on the substrate. A select gate or a main gate of the split gate memory device and a logic gate of the logic device are both made of metal, and the other gate of the split gate memory device is made of nonmetal.

Abstract translation: 半导体器件包括衬底，至少一个分离栅极存储器件和至少一个逻辑器件。 分离栅极存储器件设置在衬底上。 逻辑器件设置在衬底上。 分离栅极存储器件的选择栅极或主栅极和逻辑器件的逻辑门都由金属制成，并且分离栅极存储器件的另一个栅极由非金属制成。