公开(公告)号：US20230141093A1

公开(公告)日：2023-05-11

申请号：US18149130

申请日：2023-01-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Han-Yu LIN ,  Jhih-Rong HUANG ,  Yen-Tien TUNG ,  Tzer-Min SHEN ,  Fu-Ting YEN ,  Gary CHAN ,  Keng-Chu LIN ,  Li-Te LIN ,  Pinyen LIN

IPC: H01L21/8234 ,  H01L21/3065

CPC classification number: H01L21/823431 ,  H01L21/3065 ,  H01L21/823418

Abstract: The present disclosure describes a semiconductor structure and a method for forming the same. The method can include forming a fin structure over a substrate. The fin structure can include a channel layer and a sacrificial layer. The method can further include forming a first recess structure in a first portion of the fin structure, forming a second recess structure in the sacrificial layer of a second portion of the fin structure, forming a dielectric layer in the first and second recess structures, and performing an oxygen-free cyclic etching process to etch the dielectric layer to expose the channel layer of the second portion of the fin structure. The oxygen-free cyclic etching process can include two etching processes to selectively etch the dielectric layer over the channel layer.

公开(公告)号：US20230064393A1

公开(公告)日：2023-03-02

申请号：US17461186

申请日：2021-08-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tze-Chung LIN ,  Han-Yu LIN ,  Fang-Wei LEE ,  Li-Te LIN ,  Pinyen LIN

IPC: H01L29/66 ,  H01L21/3065 ,  H01L29/786 ,  H01L29/06

Abstract: The present disclosure describes a method that includes forming a fin structure with a stacked fin portion on a substrate. The stacked fin portion includes a first semiconductor layer and a second semiconductor layer, in which the second semiconductor layer includes germanium. The method further includes etching the fin structure to form an opening and etching a portion of the second semiconductor layer with a fluorine-containing gas through the opening.

公开(公告)号：US20200135483A1

公开(公告)日：2020-04-30

申请号：US16171875

申请日：2018-10-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Christine Y. OUYANG ,  Li-Te LIN

IPC: H01L21/308 ,  H01L21/268 ,  H01L21/033 ,  H01L21/02 ,  H01L29/66 ,  H01L29/78

Abstract: A method for forming a semiconductor structure is provided. The method includes forming a first layer over a semiconductor substrate. The first layer is made of a first material. The method also includes forming a second layer over the first layer. The second layer is made of a second material that is different from the first material. The second layer has a first opening exposing a portion of a top surface of the first layer. The method also includes heating the first layer and the second layer with a laser beam, depositing a third layer over the second layer and covering a sidewall of the first opening, and etching the first layer through the first opening to form a second opening in the first layer.

公开(公告)号：US20190164772A1

公开(公告)日：2019-05-30

申请号：US15967100

申请日：2018-04-30

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chin-Yuan TSENG ,  Yu-Tien SHEN ,  Wei-Liang LIN ,  Chih-Ming LAI ,  Kuo-Cheng CHING ,  Shi Ning JU ,  Li-Te LIN ,  Ru-Gun LIU

IPC: H01L21/311 ,  H01L21/32

Abstract: A method of reducing corner rounding during patterning of a substrate to form a prescribed pattern comprising a corner includes dividing the pattern into a first pattern and a second pattern, the first pattern forming a first edge of the corner and the second pattern forming a second edge of the corner. At least a portion of the second pattern overlaps the first pattern such that the first edge intersects with the second edge to form a corner of the prescribed pattern. The method further includes forming the first pattern in a first mask layer disposed on a substrate to expose the substrate and forming the second pattern in the first mask layer to expose the substrate. The substrate exposed through the first mask layer is then etched to obtain the pattern.

公开(公告)号：US20190139777A1

公开(公告)日：2019-05-09

申请号：US16221766

申请日：2018-12-17

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Jung-Hao CHANG ,  Chao-Hsien HUANG ,  Wen-Ting LAN ,  Shi-Ning JU ,  Li-Te LIN ,  Kuo-Cheng CHING

IPC: H01L21/308 ,  H01L21/033 ,  H01L21/311

CPC classification number: H01L21/3086 ,  H01L21/0337 ,  H01L21/31144 ,  H01L21/823431 ,  H01L29/66795

Abstract: A method includes forming a mandrel structure over a semiconductor substrate. A first spacer and a second spacer are formed alongside the mandrel structure. A mask layer is over a first portion of the first spacer, in which a second portion of the first spacer and the second spacer are exposed from the mask layer. The exposed second spacer is etched, in which etching the exposed second spacer is performed such that a polymer is formed over a top surface of the exposed second portion of the first spacer. The mask layer, the polymer, and the mandrel structure are removed. The semiconductor substrate is patterned using the first spacer.

公开(公告)号：US20240313116A1

公开(公告)日：2024-09-19

申请号：US18670123

申请日：2024-05-21

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Shu-Hao KUO ,  Jung-Hao CHANG ,  Chao-Hsien HUANG ,  Li-Te LIN ,  Kuo-Cheng CHING

IPC: H01L29/78 ,  H01L21/02 ,  H01L21/306 ,  H01L21/3065 ,  H01L21/311 ,  H01L21/762 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/092 ,  H01L27/12 ,  H01L29/06 ,  H01L29/417 ,  H01L29/66

CPC classification number: H01L29/7853 ,  H01L21/30604 ,  H01L21/3065 ,  H01L21/31116 ,  H01L21/76229 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/0649 ,  H01L29/41791 ,  H01L29/66795 ,  H01L29/66803 ,  H01L21/02532 ,  H01L21/0262 ,  H01L2029/7858

Abstract: A method includes providing a semiconductor structure including a first semiconductor substrate, an insulator layer over the first semiconductor substrate, and a second semiconductor substrate over the insulator layer; patterning the second semiconductor substrate to form a top fin portion over the insulator layer; conformally depositing a protection layer to cover the top fin portion, wherein a first portion of the protection layer is in contact with a top surface of the insulator layer; etching the protection layer to remove a second portion of the protection layer directly over the top fin portion while a third portion of the protection layer still covers a sidewall of the top fin portion; etching the insulator layer by using the third portion of the protection layer as an etch mask; and after etching the insulator layer, removing the third portion of the protection layer.

公开(公告)号：US20230089130A1

公开(公告)日：2023-03-23

申请号：US18070285

申请日：2022-11-28

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Shu-Hao KUO ,  Jung-Hao CHANG ,  Chao-Hsien HUANG ,  Li-Te LIN ,  Kuo-Cheng CHING

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/417 ,  H01L27/12 ,  H01L21/84 ,  H01L21/306 ,  H01L29/06 ,  H01L21/762 ,  H01L21/3065 ,  H01L21/311 ,  H01L21/8238 ,  H01L27/092

Abstract: A method includes providing a semiconductor structure including a first semiconductor substrate, an insulator layer over the first semiconductor substrate, and a second semiconductor substrate over the insulator layer; patterning the second semiconductor substrate to form a top fin portion over the insulator layer; conformally depositing a protection layer to cover the top fin portion, wherein a first portion of the protection layer is in contact with a top surface of the insulator layer; etching the protection layer to remove a second portion of the protection layer directly over the top fin portion while a third portion of the protection layer still covers a sidewall of the top fin portion; etching the insulator layer by using the third portion of the protection layer as an etch mask; and after etching the insulator layer, removing the third portion of the protection layer.

公开(公告)号：US20210210614A1

公开(公告)日：2021-07-08

申请号：US17207425

申请日：2021-03-19

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yi-Chen LO ,  Jung-Hao CHANG ,  Li-Te LIN ,  Pinyen LIN

IPC: H01L29/51 ,  H01L29/66 ,  H01L29/78 ,  H01L21/3065 ,  H01L21/02 ,  H01L21/28 ,  H01L21/67 ,  H01J37/00 ,  H01L27/088 ,  H01L21/8234 ,  H01L29/423 ,  H01L21/311 ,  H01L21/3213

Abstract: A method includes following steps. First and second gate electrodes are formed over a substrate, with an ILD layer between the first and second gate electrodes. A first etch operation is performed to etch the first and second gate electrodes. A sacrificial layer is formed across the etched first and second gate electrodes and the ILD layer. A second etch operation is performed to etch the sacrificial layer and the etched the first and second gate electrodes.

公开(公告)号：US20200098890A1

公开(公告)日：2020-03-26

申请号：US16559369

申请日：2019-09-03

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Zhi-Qiang WU ,  Kuo-An LIU ,  Chan-Lon YANG ,  Bharath Kumar PULICHERLA ,  Li-Te LIN ,  Chung-Cheng WU ,  Gwan-Sin CHANG ,  Pinyen LIN

IPC: H01L29/66 ,  H01L21/311 ,  H01L29/40 ,  H01L29/78 ,  H01L29/49 ,  H01L21/3213

Abstract: A method includes forming a dummy gate over a substrate. A pair of gate spacers are formed on opposite sidewalls of the dummy gate. The dummy gate is removed to form a trench between the gate spacers. A first ion beam is directed to an upper portion of the trench, while leaving a lower portion of the trench substantially free from incidence of the first ion beam. The substrate is moved relative to the first ion beam during directing the first ion beam to the trench. A gate structure is formed in the trench.

公开(公告)号：US20190165123A1

公开(公告)日：2019-05-30

申请号：US16158141

申请日：2018-10-11

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yi-Chen LO ,  Jung-Hao CHANG ,  Li-Te LIN ,  Pinyen LIN

IPC: H01L29/51 ,  H01L29/66 ,  H01L29/49 ,  H01L29/78 ,  H01L21/02 ,  H01L21/28 ,  H01L21/67 ,  H01L21/3065

Abstract: A method includes following steps. First and second gate electrodes are formed over a substrate, with an ILD layer between the first and second gate electrodes. A first etch operation is performed to etch the first and second gate electrodes. A sacrificial layer is formed across the etched first and second gate electrodes and the ILD layer. A second etch operation is performed to etch the sacrificial layer and the etched the first and second gate electrodes.