公开(公告)号：US20200066872A1

公开(公告)日：2020-02-27

申请号：US16299531

申请日：2019-03-12

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Han-Yu LIN ,  Chansyun David YANG ,  Fang-Wei LEE ,  Tze-Chung LIN ,  Li-Te LIN ,  Pinyen LIN

IPC: H01L29/66 ,  H01L29/165 ,  H01L21/02 ,  H01L29/78 ,  H01L21/768 ,  H01L21/311 ,  H01L21/321 ,  H01L29/06

Abstract: A method for forming a semiconductor device structure is provided. The method for forming a semiconductor device structure includes forming a fin structure over a substrate. The fin structure includes first semiconductor layers and second semiconductor layers alternately stacked. The method for forming the semiconductor device structure also includes removing the first semiconductor layers of the fin structure in a channel region thereby exposing the second semiconductor layers of the fin structure. The method for forming the semiconductor device structure also includes forming a dielectric material surrounding the second semiconductor layers, and treating a first portion of the dielectric material. The method for forming the semiconductor device structure also includes etching the first portion of the dielectric material to form gaps, and filling the gaps with a gate stack.

公开(公告)号：US20190165133A1

公开(公告)日：2019-05-30

申请号：US16192566

申请日：2018-11-15

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yi-Ruei JHAN ,  Yi-Lun CHEN ,  Fang-Wei LEE ,  Han-Yu LIN ,  Li-Te LIN ,  Pinyen LIN

IPC: H01L29/66 ,  H01L21/033 ,  H01L21/768 ,  H01L21/311

Abstract: In some embodiments, a method is provided. Dummy gate stacks are formed over a semiconductor substrate. An interlayer dielectric (ILD) layer is formed over the dummy gate stacks. A first portion of the ILD layer over top surfaces of the dummy gate stacks is removed, such that a second portion of the ILD layer remains between the dummy gate stacks. The dummy gate stacks are replaced with metal gate stacks. Neutral NF3 radicals into the water are applied to etch the ILD layer.

公开(公告)号：US20240194480A1

公开(公告)日：2024-06-13

申请号：US18581043

申请日：2024-02-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Ruei JHAN ,  Han-Yu LIN ,  Li-Te LIN ,  Pinyen LIN

IPC: H01L21/02 ,  H01L21/265 ,  H01L21/3105 ,  H01L29/40 ,  H01L29/66

CPC classification number: H01L21/02321 ,  H01L21/26586 ,  H01L21/31053 ,  H01L29/401 ,  H01L29/66545

Abstract: A method includes forming a dummy gate structure over a semiconductor substrate, forming a gate spacer over a sidewall of the dummy gate structure, performing a first implantation process to an upper portion of the gate spacer using a first dosage source, and performing a second implantation process to the upper portion of the gate spacer using a second dosage source including carbon. The second dosage source is different from the first dosage source.

公开(公告)号：US20220310800A1

公开(公告)日：2022-09-29

申请号：US17533575

申请日：2021-11-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Mrunal Abhijith Khaderbad ,  Wei-Yen WOON ,  Cheng-Ming LIN ,  Han-Yu LIN ,  Szu-Hua CHEN

IPC: H01L29/40 ,  H01L29/417 ,  H01L21/285

Abstract: The present disclosure describes a semiconductor device and a method for forming the semiconductor device. The method includes forming a fin structure on a substrate, forming a gate structure on the fin structure, and forming a source/drain (S/D) region on the fin structure not covered by the gate structure. The method further includes forming a contact structure on the S/D region. Forming the contact structure includes forming a transition metal chalcogenide (TMC) layer on the S/D region, and forming a contact plug on the TMC layer.

公开(公告)号：US20210313449A1

公开(公告)日：2021-10-07

申请号：US16837432

申请日：2020-04-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tze-Chung LIN ,  Han-Yu LIN ,  Li-Te LIN ,  Pinyen LIN

IPC: H01L29/66 ,  H01L21/8234 ,  H01L29/78 ,  H01L29/423

Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a plurality of first semiconductor layers and a plurality of second semiconductor layers on a substrate, and the first semiconductor layers and the second semiconductor layers are alternately stacked. The method also includes forming a dummy gate structure over the first semiconductor layers and the second semiconductor layers. The method further includes removing a portion of the first semiconductor layers and second semiconductor layers to form a trench, and removing the second semiconductor layers to form a recess between two adjacent first semiconductor layers. The method includes forming a dummy dielectric layer in the recess, and removing a portion of the dummy dielectric layer to form a cavity. The method also includes forming an inner spacer layer in the cavity.

公开(公告)号：US20230317674A1

公开(公告)日：2023-10-05

申请号：US18151160

申请日：2023-01-06

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Che Chi SHIH ,  Cheng-Ting CHUNG ,  Han-Yu LIN ,  Wei-Yen WOON ,  Szuya LIAO

IPC: H01L23/00 ,  H01L23/522 ,  H01L23/373 ,  H01L23/528

CPC classification number: H01L24/73 ,  H01L23/5226 ,  H01L23/3735 ,  H01L23/5283 ,  H01L2224/73251

Abstract: Semiconductor devices and methods are provided which facilitate improved thermal conductivity using a high-kappa dielectric bonding layer. In at least one example, a device is provided that includes a first substrate. A semiconductor device layer is disposed on the first substrate, and the semiconductor device layer includes one or more semiconductor devices. Frontside interconnect structure are disposed on the semiconductor device layer, and a bonding layer is disposed on the frontside interconnect structure. A second substrate is disposed on the bonding layer. The bonding layer has a thermal conductivity greater than 10 W/m·K.

公开(公告)号：US20230141093A1

公开(公告)日：2023-05-11

申请号：US18149130

申请日：2023-01-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Han-Yu LIN ,  Jhih-Rong HUANG ,  Yen-Tien TUNG ,  Tzer-Min SHEN ,  Fu-Ting YEN ,  Gary CHAN ,  Keng-Chu LIN ,  Li-Te LIN ,  Pinyen LIN

IPC: H01L21/8234 ,  H01L21/3065

CPC classification number: H01L21/823431 ,  H01L21/3065 ,  H01L21/823418

Abstract: The present disclosure describes a semiconductor structure and a method for forming the same. The method can include forming a fin structure over a substrate. The fin structure can include a channel layer and a sacrificial layer. The method can further include forming a first recess structure in a first portion of the fin structure, forming a second recess structure in the sacrificial layer of a second portion of the fin structure, forming a dielectric layer in the first and second recess structures, and performing an oxygen-free cyclic etching process to etch the dielectric layer to expose the channel layer of the second portion of the fin structure. The oxygen-free cyclic etching process can include two etching processes to selectively etch the dielectric layer over the channel layer.

公开(公告)号：US20230064393A1

公开(公告)日：2023-03-02

申请号：US17461186

申请日：2021-08-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tze-Chung LIN ,  Han-Yu LIN ,  Fang-Wei LEE ,  Li-Te LIN ,  Pinyen LIN

IPC: H01L29/66 ,  H01L21/3065 ,  H01L29/786 ,  H01L29/06

Abstract: The present disclosure describes a method that includes forming a fin structure with a stacked fin portion on a substrate. The stacked fin portion includes a first semiconductor layer and a second semiconductor layer, in which the second semiconductor layer includes germanium. The method further includes etching the fin structure to form an opening and etching a portion of the second semiconductor layer with a fluorine-containing gas through the opening.

公开(公告)号：US20220020644A1

公开(公告)日：2022-01-20

申请号：US17143698

申请日：2021-01-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Han-Yu LIN ,  Jhih-Rong Huang ,  Yen-Tien Tung ,  Tzer-Min Shen ,  Fu-Ting Yen ,  Gary Chan ,  Keng-Chu Lin ,  Li-Te Lin ,  Pinyen Lin

IPC: H01L21/8234 ,  H01L21/3065

Abstract: The present disclosure describes a semiconductor structure and a method for forming the same. The method can include forming a fin structure over a substrate. The fin structure can include a first channel layer and a sacrificial layer. The method can further include forming a first recess structure in a first portion of the fin structure, forming a second recess structure in the sacrificial layer of a second portion of the fin structure, forming a dielectric layer in the first and second recess structures, and performing an oxygen-free cyclic etching process to etch the dielectric layer to expose the channel layer of the second portion of the fin structure. The process of performing the oxygen-free cyclic etching process can include performing a first etching process to selectively etch the dielectric layer over the channel layer of the second portion of the fin structure with a first etching selectivity, and performing a second etching process to selectively etch the dielectric layer over the channel layer of the second portion of fin structure with a second etching selectivity greater than the first etching selectivity