公开(公告)号：US20210193511A1

公开(公告)日：2021-06-24

申请号：US16721762

申请日：2019-12-19

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Sung-Li WANG ,  Shuen-Shin LIANG ,  Yu-Yun PENG ,  Fang-Wei LEE ,  Chia-Hung CHU ,  Mrunal Abhijith KHADERBAD ,  Keng-Chu LIN

IPC: H01L21/768 ,  H01L21/306

Abstract: A multi-layer interconnect structure with a self-aligning barrier structure and a method for fabricating the same is disclosed. For example, the method includes forming a via through an interlayer dielectric (ILD) layer, an etch stop layer (ESL), and a contact structure, pre-cleaning the via with a metal halide, forming a barrier structure on the contact structure in-situ during the pre-cleaning of the via with the metal halide, and depositing a second metal in the via on top of the barrier structure.

公开(公告)号：US20230017512A1

公开(公告)日：2023-01-19

申请号：US17377861

申请日：2021-07-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tze-Chung LIN ,  Pinyen LIN ,  Fang-Wei LEE ,  Li-Te LIN ,  Han-yu LIN

IPC: H01L29/417 ,  H01L29/423 ,  H01L29/786 ,  H01L29/06 ,  H01L21/3065 ,  H01L29/66

Abstract: The present disclosure describes a method includes forming a fin structure including a fin bottom portion and a stacked fin portion on a substrate. The stacked fin portion includes a first semiconductor layer and a second semiconductor layer, in which the first semiconductor layer includes germanium. The method further includes etching the fin structure to form an opening, delivering a primary etchant and a germanium-containing gas to the fin structure through the opening, and etching a portion of the second semiconductor layer in the opening with the primary etchant and the germanium-containing gas.

公开(公告)号：US20210226057A1

公开(公告)日：2021-07-22

申请号：US16744480

申请日：2020-01-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Hung CHU ,  Sung-Li WANG ,  Fang-Wei LEE ,  Jung-Hao CHANG ,  Mrunal Abhijith KHADERBAD ,  Keng-Chu LIN

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/08 ,  H01L29/45 ,  H01L21/311 ,  H01L29/417

Abstract: A method for forming a fin field effect transistor device structure includes forming a fin structure over a substrate. The method also includes forming a gate structure across the fin structure. The method also includes growing a source/drain epitaxial structure over the fin structure. The method also includes depositing a first dielectric layer surrounding the source/drain epitaxial structure. The method also includes forming a contact structure in the first dielectric layer over the source/drain epitaxial structure. The method also includes depositing a second dielectric layer over the first dielectric layer. The method also includes forming a hole in the second dielectric layer to expose the contact structure. The method also includes etching the contact structure to enlarge the hole in the contact structure. The method also includes filling the hole with a conductive material.

公开(公告)号：US20240243009A1

公开(公告)日：2024-07-18

申请号：US18618815

申请日：2024-03-27

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Sung-Li WANG ,  Shuen-Shin LIANG ,  Yu-Yun PENG ,  Fang-Wei LEE ,  Chia-Hung CHU ,  Mrunal Abhijith KHADERBAD ,  Keng-Chu LIN

IPC: H01L21/768 ,  H01L21/02 ,  H01L21/285 ,  H01L21/306 ,  H01L21/8234 ,  H01L23/522 ,  H01L23/532

CPC classification number: H01L21/76816 ,  H01L21/02063 ,  H01L21/02068 ,  H01L21/28562 ,  H01L21/30604 ,  H01L21/76805 ,  H01L21/76814 ,  H01L21/76834 ,  H01L21/76849 ,  H01L21/7685 ,  H01L21/76856 ,  H01L21/76864 ,  H01L21/76879 ,  H01L21/76883 ,  H01L21/76897 ,  H01L21/823475 ,  H01L23/5226 ,  H01L23/53223 ,  H01L23/53252 ,  H01L23/53266

Abstract: A device includes source/drain regions, a gate structure, a source/drain contact, and a tungsten structure. The source/drain regions are over a substrate. The gate structure is between the source/drain regions. The source/drain contact is over one of the source/drain regions. The tungsten structure is over the source/drain contact. The tungsten structure includes a lower portion and an upper portion above the lower portion. The upper portion has opposite sidewalls respectively set back from opposite sidewalls of the lower portion of the tungsten structure.

公开(公告)号：US20230064393A1

公开(公告)日：2023-03-02

申请号：US17461186

申请日：2021-08-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tze-Chung LIN ,  Han-Yu LIN ,  Fang-Wei LEE ,  Li-Te LIN ,  Pinyen LIN

IPC: H01L29/66 ,  H01L21/3065 ,  H01L29/786 ,  H01L29/06

Abstract: The present disclosure describes a method that includes forming a fin structure with a stacked fin portion on a substrate. The stacked fin portion includes a first semiconductor layer and a second semiconductor layer, in which the second semiconductor layer includes germanium. The method further includes etching the fin structure to form an opening and etching a portion of the second semiconductor layer with a fluorine-containing gas through the opening.

公开(公告)号：US20220139773A1

公开(公告)日：2022-05-05

申请号：US17575444

申请日：2022-01-13

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Sung-Li WANG ,  Shuen-Shin LIANG ,  Yu-Yun PENG ,  Fang-Wei LEE ,  Chia-Hung CHU ,  Mrunal Abhijith KHADERBAD ,  Keng-Chu LIN

IPC: H01L21/768 ,  H01L21/306 ,  H01L23/522 ,  H01L21/285 ,  H01L21/02 ,  H01L23/532

Abstract: An IC structure includes a transistor, a source/drain contact, a metal oxide layer, a non-metal oxide layer, a barrier structure, and a via. The transistor includes a gate structure and source/drain regions on opposite sides of the gate structure. The source/drain contact is over one of the source/drain regions. The metal oxide layer is over the source/drain contact. The non-metal oxide layer is over the metal oxide layer. The barrier structure is over the source/drain contact. The barrier structure forms a first interface with the metal oxide layer and a second interface with the non-metal oxide layer, and the second interface is laterally offset from the first interface. The via extends through the non-metal oxide layer to the barrier structure.

公开(公告)号：US20200066872A1

公开(公告)日：2020-02-27

申请号：US16299531

申请日：2019-03-12

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Han-Yu LIN ,  Chansyun David YANG ,  Fang-Wei LEE ,  Tze-Chung LIN ,  Li-Te LIN ,  Pinyen LIN

IPC: H01L29/66 ,  H01L29/165 ,  H01L21/02 ,  H01L29/78 ,  H01L21/768 ,  H01L21/311 ,  H01L21/321 ,  H01L29/06

Abstract: A method for forming a semiconductor device structure is provided. The method for forming a semiconductor device structure includes forming a fin structure over a substrate. The fin structure includes first semiconductor layers and second semiconductor layers alternately stacked. The method for forming the semiconductor device structure also includes removing the first semiconductor layers of the fin structure in a channel region thereby exposing the second semiconductor layers of the fin structure. The method for forming the semiconductor device structure also includes forming a dielectric material surrounding the second semiconductor layers, and treating a first portion of the dielectric material. The method for forming the semiconductor device structure also includes etching the first portion of the dielectric material to form gaps, and filling the gaps with a gate stack.

公开(公告)号：US20190165133A1

公开(公告)日：2019-05-30

申请号：US16192566

申请日：2018-11-15

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yi-Ruei JHAN ,  Yi-Lun CHEN ,  Fang-Wei LEE ,  Han-Yu LIN ,  Li-Te LIN ,  Pinyen LIN

IPC: H01L29/66 ,  H01L21/033 ,  H01L21/768 ,  H01L21/311

Abstract: In some embodiments, a method is provided. Dummy gate stacks are formed over a semiconductor substrate. An interlayer dielectric (ILD) layer is formed over the dummy gate stacks. A first portion of the ILD layer over top surfaces of the dummy gate stacks is removed, such that a second portion of the ILD layer remains between the dummy gate stacks. The dummy gate stacks are replaced with metal gate stacks. Neutral NF3 radicals into the water are applied to etch the ILD layer.