公开(公告)号：US20130239070A1

公开(公告)日：2013-09-12

申请号：US13867154

申请日：2013-04-22

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Cheng-I HUANG ,  Hsiao-Shu CHAO ,  Yi-Kan CHENG

IPC: G06F17/50

CPC classification number: G06F17/50 ,  G03F1/36 ,  G03F1/38 ,  G06F17/5081 ,  G06F2217/84 ,  H01L27/0207

Abstract: A method includes performing a place and route operation using an electronic design automation tool to generate a preliminary layout for a photomask to be used to form a circuit pattern of a semiconductor device. The place and route operation is constrained by a plurality of single patterning spacer technique (SPST) routing rules. Dummy conductive fill patterns are emulated within the EDA tool using an RC extraction tool to predict locations and sizes of dummy conductive fill patterns to be added to the preliminary layout of the photomask. An RC timing analysis of the circuit pattern is performed within the EDA tool, based on the preliminary layout and the emulated dummy conductive fill patterns.

Abstract translation: 一种方法包括使用电子设计自动化工具执行位置和路线操作，以产生用于形成半导体器件的电路图案的光掩模的初步布局。 位置和路线操作受到多个单一图案化间隔物技术（SPST）路由规则约束。 使用RC提取工具在EDA工具内模拟虚拟导电填充图案，以预测要添加到光掩模的初步布局的虚拟导电填充图案的位置和大小。 基于初步布局和仿真虚拟导电填充图案，在EDA工具中执行电路图案的RC定时分析。

公开(公告)号：US20240395795A1

公开(公告)日：2024-11-28

申请号：US18791291

申请日：2024-07-31

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Cheng-I HUANG ,  Ting-Wei CHIANG ,  Shih-Chi FU ,  Sheng-Fang CHENG ,  Jung-Chan YANG

IPC: H01L27/02 ,  G06F30/39 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/66

Abstract: A semiconductor device includes a first fin, a first continuous fin and continuous gates. The first fin is formed on a substrate, and includes first and second portions that are spaced apart by a first recess. A side of the first portion and a side of the second portion are located at two sides of the first recess, respectively. The first continuous fin is formed on the substrate, and extends along the first portion, the first recess and the second portion. The continuous gates are formed on the substrate, and arranged to intersect the first continuous fin and the first fin in a layout view. A first number of the continuous gates are disposed across the first recess and each of the first number of the continuous gates is disposed between the two sides of the first recess in a layout view. A method is also disclosed herein.

公开(公告)号：US20190103393A1

公开(公告)日：2019-04-04

申请号：US16206746

申请日：2018-11-30

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Cheng-I HUANG ,  Ting-Wei CHIANG ,  Shih-Chi FU ,  Sheng-Fang CHENG ,  Jung-Chan YANG

IPC: H01L27/02 ,  G06F17/50 ,  H01L29/66 ,  H01L27/088

Abstract: A method includes the operations below. A first and second layout patterns corresponding to a first and second area are placed. Third layout patterns corresponding to a first continuous fin over the first area and second area, and corresponding to a second fin including separate portions spaced apart by a first recess over the first area are placed. A fourth layout pattern, corresponding to a dummy gate, at the recess portion and between the first layout pattern and the second layout pattern, is placed to generate a layout design of a semiconductor device. A side of the second area facing the first recess is substantially flat, and the semiconductor device is fabricated by a tool based on the layout design. A first length of the first continuous fin is equal to a sum of a second length of the second fin and a third length of the first recess.

公开(公告)号：US20210082904A1

公开(公告)日：2021-03-18

申请号：US17107311

申请日：2020-11-30

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Cheng-I HUANG ,  Ting-Wei CHIANG ,  Shih-Chi FU ,  Sheng-Fang CHENG ,  Jung-Chan YANG

IPC: H01L27/02 ,  G06F30/39 ,  H01L27/088 ,  H01L29/66

Abstract: A semiconductor device includes a first fin, a first continuous fin and continuous gates. The first fin is formed on a substrate, and includes first and second portions that are spaced apart by a first recess. A side of the first portion and a side of the second portion are located at two sides of the first recess, respectively. The first continuous fin is formed on the substrate, and extends along the first portion, the first recess and the second portion. The continuous gates are formed on the substrate, and arranged to intersect the first continuous fin and the first fin in a layout view. A first number of the continuous gates are disposed across the first recess and each of the first number of the continuous gates is disposed between the two sides of the first recess in a layout view. A method is also disclosed herein.

公开(公告)号：US20200004137A1

公开(公告)日：2020-01-02

申请号：US16287450

申请日：2019-02-27

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Ru-Gun LIU ,  Chin-Hsiang LIN ,  Cheng-I HUANG ,  Chih-Ming LAI ,  Lai Chien WEN ,  Ken-Hsien HSIEH ,  Shih-Ming CHANG ,  Yuan-Te HOU

IPC: G03F1/42 ,  G03F1/50 ,  G03F1/68 ,  G03F7/20

Abstract: A photo mask for manufacturing a semiconductor device includes a first pattern extending in a first direction, a second pattern extending in the first direction and aligned with the first pattern, and a sub-resolution pattern extending in the first direction, disposed between an end of the first pattern and an end of the second pattern. A width of the first pattern and a width of the second pattern are equal to each other, and the first pattern and the second pattern are for separate circuit elements in the semiconductor device.

公开(公告)号：US20170179105A1

公开(公告)日：2017-06-22

申请号：US15172020

申请日：2016-06-02

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Cheng-I HUANG ,  Ting-Wei CHIANG ,  Shih-Chi FU ,  Sheng-Fang CHENG ,  Jung-Chan YANG

IPC: H01L27/02 ,  H01L21/8234 ,  H01L29/66 ,  H01L27/088

CPC classification number: H01L27/0207 ,  G06F17/5068 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/66545

Abstract: A semiconductor device includes a substrate and fins. The fins are formed on a first area and a second area of the substrate. The first area includes a first recess. The second area is located with respect to the first area. The first recess is disposed at a side of the first area, and faces the second area. A projection area of the first recess on a side of the second area is substantially flat.

公开(公告)号：US20150363541A1

公开(公告)日：2015-12-17

申请号：US14833364

申请日：2015-08-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yen-Hung LIN ,  Cheng-I HUANG ,  Chin-Chang HSU ,  Hung Lung LIN

IPC: G06F17/50

CPC classification number: G06F17/5081 ,  G06F2217/06

Abstract: A method includes accessing data representing a layout of a layer of an integrated circuit (IC) having a plurality of polygons defining circuit patterns to be divided among a number (N) of photomasks over a single layer of a semiconductor substrate, where N is greater than two. The method further includes inputting a conflict graph having a plurality of vertices, identifying a first and second vertex, each of which is connected to a third and fourth vertex where the third and fourth vertices are connected to a same edge of a conflict graph, and merging the first and second vertices to form a reduced graph. The method further includes detecting at least one or more vertex in the reduced having a conflict. In one aspect, the method resolves the detected conflict by performing one of pattern shifting, stitch inserting, or re-routing.

Abstract translation: 一种方法包括访问表示具有多个多边形的集成电路（IC）的层的布局的数据，该多个多边形定义要在半导体衬底的单个层上的数个（N个）光掩模中划分的电路图案，其中N较大 比两个。 该方法还包括输入具有多个顶点的冲突图，识别第一和第二顶点，每个顶点连接到第三和第四顶点，其中第三和第四顶点连接到冲突图的相同边缘;以及 合并第一和第二顶点以形成缩小图。 所述方法还包括检测所述缩小的至少一个或多个顶点具有冲突。 在一个方面，该方法通过执行图案移位，针迹插入或重新路由之一来解决检测到的冲突。