公开(公告)号：US11900043B2

公开(公告)日：2024-02-13

申请号：US17701520

申请日：2022-03-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sooyong Lee ,  Dongho Kim ,  Sangwook Kim ,  Jungmin Kim ,  Seunghune Yang ,  Jeeyong Lee ,  Changmook Yim ,  Yangwoo Heo

IPC: G06F30/30 ,  G03F7/00 ,  G06F30/398 ,  G06F30/392 ,  G06F30/27 ,  G06F119/18

CPC classification number: G06F30/398 ,  G03F7/705 ,  G03F7/70441 ,  G06F30/27 ,  G06F30/392 ,  G06F2119/18

Abstract: Disclosed is an operating method of an electronic device which includes receiving a design layout for manufacturing the semiconductor device, generating a first layout by performing machine learning-based process proximity correction (PPC), generating a second layout by performing optical proximity correction (OPC), and outputting the second layout for a semiconductor process. The generating of the first layout includes generating a first after cleaning inspection (ACI) layout by executing a machine learning-based process proximity correction module on the design layout, generating a second after cleaning inspection layout by adjusting the design layout based on a difference of the first after cleaning inspection layout and the design layout and executing the process proximity correction module on the adjusted layout, and outputting the adjusted layout as the first layout, when a difference between the second after cleaning inspection layout and the design layout is smaller than or equal to a threshold value.

公开(公告)号：US20240362395A1

公开(公告)日：2024-10-31

申请号：US18394330

申请日：2023-12-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yangwoo Heo ,  Bayram Yenikaya ,  Xin Li ,  Sangwook Kim

IPC: G06F30/398 ,  G03F1/36

CPC classification number: G06F30/398 ,  G03F1/36

Abstract: A layout correction method for a semiconductor device includes receiving a design layout including at least a target layer and a reference layer, detecting target edges including target patterns in the target layer, and detecting reference edges including reference patterns in the reference layer, determining a dissection point in a section intersecting a space between reference patterns on a target edge having three or more intersecting reference edges, generating segments by dissecting the target edges based on dissection points set for the target edges, setting an evaluation point at an intermediate point of a section intersecting a reference pattern in a segment intersecting the reference pattern, among the segments, determining a movement amount of segments having evaluation points set on the segments by inputting a feature measured at the evaluation points to a layout correction model, and generating a corrected layout by moving the segments based on the movement amount.

公开(公告)号：US20240220700A1

公开(公告)日：2024-07-04

申请号：US18210836

申请日：2023-06-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yangwoo Heo ,  Majd Kuteifan ,  Mindy Lee ,  SOOYONG LEE ,  JEEYONG LEE

IPC: G06F30/392

CPC classification number: G06F30/392 ,  G06F2119/02

Abstract: Provided is a process model generating method including: obtaining a target layout for a process of a semiconductor device and a plurality of sublayers representing a substructure of the semiconductor device; determining a lateral feature and a vertical feature of the target layout; and generating a correction model for the target layout based on the lateral feature and the vertical feature.