公开(公告)号：US20210225716A1

公开(公告)日：2021-07-22

申请号：US16992271

申请日：2020-08-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： SOOYONG LEE ,  MINCHEOL KANG ,  BONGSOO KANG ,  JEEYONG LEE

IPC: H01L21/66 ,  H01L27/11556 ,  H01L27/11582 ,  G06N3/04 ,  G06N3/08

Abstract: A method of manufacturing a semiconductor device includes forming a lower mold having lower layers stacked on a substrate and lower channel structures passing therethrough; forming an upper mold including upper layers stacked on the lower mold and upper channel structures passing therethrough; removing the upper mold to expose an upper surface of the lower mold; separating an upper original image in which traces of the upper channel structures are displayed, and a lower original image in which the lower channel structures are displayed, from an original image capturing the upper surface of the lower mold; inputting the upper original image into a learned neural network to acquire an upper restored image in which cross sections of the upper channel structures are displayed; and comparing the upper restored image with the lower original image to verify an alignment state of the upper and lower molds.

公开(公告)号：US20240220700A1

公开(公告)日：2024-07-04

申请号：US18210836

申请日：2023-06-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yangwoo Heo ,  Majd Kuteifan ,  Mindy Lee ,  SOOYONG LEE ,  JEEYONG LEE

IPC: G06F30/392

CPC classification number: G06F30/392 ,  G06F2119/02

Abstract: Provided is a process model generating method including: obtaining a target layout for a process of a semiconductor device and a plurality of sublayers representing a substructure of the semiconductor device; determining a lateral feature and a vertical feature of the target layout; and generating a correction model for the target layout based on the lateral feature and the vertical feature.