公开(公告)号：US20210225716A1

公开(公告)日：2021-07-22

申请号：US16992271

申请日：2020-08-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： SOOYONG LEE ,  MINCHEOL KANG ,  BONGSOO KANG ,  JEEYONG LEE

IPC: H01L21/66 ,  H01L27/11556 ,  H01L27/11582 ,  G06N3/04 ,  G06N3/08

Abstract: A method of manufacturing a semiconductor device includes forming a lower mold having lower layers stacked on a substrate and lower channel structures passing therethrough; forming an upper mold including upper layers stacked on the lower mold and upper channel structures passing therethrough; removing the upper mold to expose an upper surface of the lower mold; separating an upper original image in which traces of the upper channel structures are displayed, and a lower original image in which the lower channel structures are displayed, from an original image capturing the upper surface of the lower mold; inputting the upper original image into a learned neural network to acquire an upper restored image in which cross sections of the upper channel structures are displayed; and comparing the upper restored image with the lower original image to verify an alignment state of the upper and lower molds.

公开(公告)号：US20230325577A1

公开(公告)日：2023-10-12

申请号：US17903070

申请日：2022-09-06

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： SEORIM MOON ,  BONHYUN GU ,  SOOYONG LEE

IPC: G06F30/398

CPC classification number: G06F30/398 ,  G06F2119/02

Abstract: A method of manufacturing a semiconductor chip includes; generating a layout pattern, performing Process Proximity Correction (PPC) on the layout pattern to generate a PPC layout pattern, wherein the performing of PPC includes verifying the PPC layout pattern using machine learning, performing Optical Proximity Correction (OPC) on the PPC layout pattern to generate an OPC layout pattern, manufacturing a mask using the OPC layout pattern, and manufacturing a semiconductor chip using the mask.

公开(公告)号：US20240377988A1

公开(公告)日：2024-11-14

申请号：US18535027

申请日：2023-12-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： SOOYONG LEE ,  JAE HYUN CHOI

IPC: G06F3/06

Abstract: A memory device may include a memory cell array including first to fourth memory cells respectively connected to first to fourth word lines, a sense amplifier including a first sensing circuit that is configured to generate a first weighted sum based on a first weight stored in the first memory cell and a second weight stored in the third memory cell, in response to an activation of the first and third word lines at a first time point, an input and output circuit that is configured to output the first weighted sum to an external device in response to a first read command, and a restore circuit that is configured to perform a restore operation for storing a first data item stored in the second memory cell to the first memory cell and for storing a second data item stored in the fourth memory cell to the third memory cell after the first time point.

公开(公告)号：US20240220700A1

公开(公告)日：2024-07-04

申请号：US18210836

申请日：2023-06-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yangwoo Heo ,  Majd Kuteifan ,  Mindy Lee ,  SOOYONG LEE ,  JEEYONG LEE

IPC: G06F30/392

CPC classification number: G06F30/392 ,  G06F2119/02

Abstract: Provided is a process model generating method including: obtaining a target layout for a process of a semiconductor device and a plurality of sublayers representing a substructure of the semiconductor device; determining a lateral feature and a vertical feature of the target layout; and generating a correction model for the target layout based on the lateral feature and the vertical feature.