公开(公告)号：US20240040772A1

公开(公告)日：2024-02-01

申请号：US18332413

申请日：2023-06-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Minyoung LEE ,  Sungjin YEO ,  Wonseok YOO ,  Jaemin WOO ,  Kyeongock CHONG ,  Myunghun JUNG ,  Yoongi HONG

IPC: H10B12/00

CPC classification number: H10B12/482 ,  H10B12/0335 ,  H10B12/315

Abstract: A semiconductor device may include a bit line structure, a first spacer, and a second spacer on a substrate. The bit line structure may include a conductive structure and an insulation structure stacked in a vertical direction substantially perpendicular to an upper surface of the substrate. The first spacer and the second spacer may be stacked in a horizontal direction on a sidewall of the bit line structure. The horizontal direction may be substantially parallel to the upper surface of the substrate. The conductive structure may include a nitrogen-containing conductive portion at a lateral portion thereof. The first spacer may contact the nitrogen-containing conductive portion.

公开(公告)号：US20220093387A1

公开(公告)日：2022-03-24

申请号：US17222195

申请日：2021-04-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dain LEE ,  Yoongoo KANG ,  Wonseok YOO ,  Jinwon MA ,  Kyungwook PARK ,  Changwoo SEO ,  Suyoun SONG

IPC: H01L21/02 ,  C23C16/455

Abstract: A semiconductor device manufacturing method includes loading a semiconductor substrate into a chamber, the semiconductor substrate including a silicon oxide film, depositing a seed layer on the silicon oxide film by supplying a first silicon source material, supplying a purge gas on the seed layer, depositing a protective layer on the seed layer by repeating a first cycle, the first cycle including supplying a base source material layer and subsequently supplying the first silicon source material, and depositing a silicon nitride film on the protective layer by repeating a second cycle, the second cycle including supplying a second silicon source material and subsequently supplying a nitrogen source material.

公开(公告)号：US20220246620A1

公开(公告)日：2022-08-04

申请号：US17723218

申请日：2022-04-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yoongoo KANG ,  Wonseok YOO ,  Hokyun AN ,  Kyungwook PARK ,  Dain LEE

IPC: H01L27/108 ,  G11C5/06 ,  H01L29/06

Abstract: A DRAM device includes an isolation region defining source and drain regions in a substrate, a first bit line structure connected to the source region, a second bit line structure disposed on the isolation region, an inner spacer vertically extending on a first sidewall of the first bit line structure, an air gap is between the inner spacer and an outer spacer, a storage contact between the first and second bit line structures and connected to the drain region, a landing pad structure vertically on the storage contact, and a storage structure vertically on the landing pad structure. The sealing layer seals a top of the first air gap. The sealing layer includes a first sealing layer on a first sidewall of a pad isolation trench, and a second sealing layer on a second sidewall of the pad isolation trench and separated from the first sealing layer.

公开(公告)号：US20210066304A1

公开(公告)日：2021-03-04

申请号：US16837274

申请日：2020-04-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yoongoo KANG ,  Wonseok YOO ,  Hokyun AN ,  Kyungwook PARK ,  Dain LEE

IPC: H01L27/108 ,  G11C5/06 ,  H01L29/06

Abstract: A DRAM device includes an isolation region defining source and drain regions in a substrate, a first bit line structure connected to the source region, a second bit line structure disposed on the isolation region, an inner spacer vertically extending on a first sidewall of the first bit line structure, an air gap is between the inner spacer and an outer spacer, a storage contact between the first and second bit line structures and connected to the drain region, a landing pad structure vertically on the storage contact, and a storage structure vertically on the landing pad structure. The sealing layer seals a top of the first air gap. The sealing layer includes a first sealing layer on a first sidewall of a pad isolation trench, and a second sealing layer on a second sidewall of the pad isolation trench and separated from the first sealing layer.

公开(公告)号：US20140183434A1

公开(公告)日：2014-07-03

申请号：US14064826

申请日：2013-10-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hanjin LIM ,  Wonseok YOO ,  Insang JEON ,  Seokwoo NAM ,  Kongsoo LEE ,  Jaejong HAN

IPC: H01L27/24 ,  H01L29/78 ,  H01L29/872

CPC classification number: H01L27/2463 ,  H01L21/2652 ,  H01L21/28518 ,  H01L21/76814 ,  H01L21/76834 ,  H01L23/485 ,  H01L27/2409 ,  H01L29/0847 ,  H01L29/167 ,  H01L29/401 ,  H01L29/456 ,  H01L29/8613 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/1273 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Semiconductor devices, and methods of fabricating the same, include a metal-containing layer on a semiconductor layer, and a barrier-lowering portion between the metal-containing layer and the semiconductor layer. The barrier-lowering portion lowers a Schottky barrier height between the metal-containing layer and the semiconductor layer below a Schottky barrier height between a metal silicide layer and the semiconductor layer.

Abstract translation: 半导体器件及其制造方法包括半导体层上的含金属层和金属含有层与半导体层之间的阻挡降低部。 阻挡降低部将金属含有层与半导体层之间的肖特基势垒高度降低到金属硅化物层与半导体层之间的肖特基势垒高度以下。

公开(公告)号：US20230422487A1

公开(公告)日：2023-12-28

申请号：US18149800

申请日：2023-01-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jonghyeok KIM ,  Jamin KOO ,  Beom Seo KIM ,  Wonseok YOO

IPC: H10B12/00

CPC classification number: H10B12/482 ,  H10B12/315 ,  H10B12/34 ,  H10B12/485 ,  H10B12/02

Abstract: A semiconductor memory device including an active pattern defined by a device isolation pattern, a bit line extending in a first direction on the device isolation pattern and the active pattern, a bit line capping pattern including a first capping pattern, a second capping pattern, and a third capping pattern sequentially stacked on an upper surface of the bit line, and a shield pattern covering one side of the bit line may be provided. An upper surface of the shield pattern may be at a height lower than an upper surface of the first capping pattern.