公开(公告)号：US20240040772A1

公开(公告)日：2024-02-01

申请号：US18332413

申请日：2023-06-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Minyoung LEE ,  Sungjin YEO ,  Wonseok YOO ,  Jaemin WOO ,  Kyeongock CHONG ,  Myunghun JUNG ,  Yoongi HONG

IPC: H10B12/00

CPC classification number: H10B12/482 ,  H10B12/0335 ,  H10B12/315

Abstract: A semiconductor device may include a bit line structure, a first spacer, and a second spacer on a substrate. The bit line structure may include a conductive structure and an insulation structure stacked in a vertical direction substantially perpendicular to an upper surface of the substrate. The first spacer and the second spacer may be stacked in a horizontal direction on a sidewall of the bit line structure. The horizontal direction may be substantially parallel to the upper surface of the substrate. The conductive structure may include a nitrogen-containing conductive portion at a lateral portion thereof. The first spacer may contact the nitrogen-containing conductive portion.