公开(公告)号：US20230237236A1

公开(公告)日：2023-07-27

申请号：US17945724

申请日：2022-09-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jonghyeok KIM ,  Myungjin Choi ,  Yoongi Choi

IPC: G06F30/392 ,  G06F30/394 ,  G06F30/327

CPC classification number: G06F30/392 ,  G06F30/394 ,  G06F30/327

Abstract: A method of designing a layout of a semiconductor integrated circuit, including receiving input data defining the semiconductor integrated circuit; determining a first layout of the semiconductor integrated circuit by performing a placement and routing (P&R) procedure based on the input data, wherein the first layout includes a plurality of blocks, a plurality of standard cells, a plurality of power wirings, a plurality of ground wirings, a plurality of clock wirings, and a plurality of signal wirings; selecting a target region of the first layout, wherein the target region is capable of accommodating at least one additional power wiring and at least one additional ground wiring; and determining a second layout of the semiconductor integrated circuit by modifying the first layout to include the at least one additional power wiring and the at least one additional ground wiring in the target region.

公开(公告)号：US20230422487A1

公开(公告)日：2023-12-28

申请号：US18149800

申请日：2023-01-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jonghyeok KIM ,  Jamin KOO ,  Beom Seo KIM ,  Wonseok YOO

IPC: H10B12/00

CPC classification number: H10B12/482 ,  H10B12/315 ,  H10B12/34 ,  H10B12/485 ,  H10B12/02

Abstract: A semiconductor memory device including an active pattern defined by a device isolation pattern, a bit line extending in a first direction on the device isolation pattern and the active pattern, a bit line capping pattern including a first capping pattern, a second capping pattern, and a third capping pattern sequentially stacked on an upper surface of the bit line, and a shield pattern covering one side of the bit line may be provided. An upper surface of the shield pattern may be at a height lower than an upper surface of the first capping pattern.

公开(公告)号：US20220115377A1

公开(公告)日：2022-04-14

申请号：US17331725

申请日：2021-05-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyokyoung KIM ,  Jamin KOO ,  Jonghyeok KIM ,  Daeyoung MOON

IPC: H01L27/108 ,  H01L29/423

Abstract: A semiconductor device includes a substrate including an isolation layer pattern and an active pattern, a buffer insulation layer pattern on the substrate, a polysilicon structure on the active pattern and the buffer insulation layer pattern, the polysilicon structure contacting a portion of the active pattern, and the polysilicon structure extending in a direction parallel to an upper surface of the substrate, a first diffusion barrier layer pattern on an upper surface of the polysilicon structure, the first diffusion barrier layer pattern including polysilicon doped with at least carbon, a second diffusion barrier layer pattern on the first diffusion barrier layer pattern, the second diffusion barrier layer pattern including at least a metal, and a first metal pattern and a first capping layer pattern stacked on the second diffusion barrier layer pattern.

公开(公告)号：US20240172416A1

公开(公告)日：2024-05-23

申请号：US18240512

申请日：2023-08-31

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jonghyeok KIM ,  Kang In KIM ,  Kyuwan KIM ,  Min-Cheol KIM ,  Youngseok KIM ,  Taewoong OH

IPC: H10B12/00

CPC classification number: H10B12/315 ,  H10B12/482 ,  H10B12/485 ,  H10B12/488

Abstract: A semiconductor device includes a substrate having a substrate groove extending in a first direction, a gate insulating layer conformally covering an inner wall of the substrate groove, a metal-containing pattern on the gate insulating layer and filling a lower portion of the substrate groove, a silicon pattern on the metal-containing pattern in the substrate groove, and a word line capping pattern on the silicon pattern in the substrate groove, wherein the silicon pattern includes a first silicon pattern covering an upper surface of the metal-containing pattern and a sidewall of the gate insulating layer and having a pattern groove formed thereon and a second silicon pattern filling the pattern groove, the first silicon pattern having a first impurity concentration, and the second silicon pattern having a second impurity concentration less than the first impurity concentration.

公开(公告)号：US20240005079A1

公开(公告)日：2024-01-04

申请号：US18319049

申请日：2023-05-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jonghyeok KIM

IPC: G06F30/394 ,  G06F30/36

CPC classification number: G06F30/394 ,  G06F30/36 ,  G06F2113/18

Abstract: A method of arranging power lines to be applied to a memory device including a plurality of layers, wherein, in each of the plurality of layers, a plurality of power lines and a plurality of signal lines are arranged along a plurality of track lines arranged side by side to be separated from each other in a first direction or a second direction that is perpendicular to the first direction is provided. The method includes identifying a first track line on which a plurality of power lines are arranged, moving at least one of the plurality of power lines to a second track line adjacent to the first track line, and electrically connecting the moved at least one power line on the second track line.