公开(公告)号：US20240172416A1

公开(公告)日：2024-05-23

申请号：US18240512

申请日：2023-08-31

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jonghyeok KIM ,  Kang In KIM ,  Kyuwan KIM ,  Min-Cheol KIM ,  Youngseok KIM ,  Taewoong OH

IPC: H10B12/00

CPC classification number: H10B12/315 ,  H10B12/482 ,  H10B12/485 ,  H10B12/488

Abstract: A semiconductor device includes a substrate having a substrate groove extending in a first direction, a gate insulating layer conformally covering an inner wall of the substrate groove, a metal-containing pattern on the gate insulating layer and filling a lower portion of the substrate groove, a silicon pattern on the metal-containing pattern in the substrate groove, and a word line capping pattern on the silicon pattern in the substrate groove, wherein the silicon pattern includes a first silicon pattern covering an upper surface of the metal-containing pattern and a sidewall of the gate insulating layer and having a pattern groove formed thereon and a second silicon pattern filling the pattern groove, the first silicon pattern having a first impurity concentration, and the second silicon pattern having a second impurity concentration less than the first impurity concentration.

公开(公告)号：US20230209805A1

公开(公告)日：2023-06-29

申请号：US18116883

申请日：2023-03-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Daeyoung MOON ,  Jamin KOO ,  Kyuwan KIM ,  Kisoo PARK

IPC: H10B12/00

CPC classification number: H10B12/315 ,  H10B12/033 ,  H10B12/34 ,  H10B12/482 ,  H10B12/485

Abstract: A semiconductor memory device includes a device isolation pattern on a substrate to define an active region, a word line in the substrate, to intersect the active region, a first dopant region in the active region as at a first side of the word line, a second dopant region in the active region at a second side of the word line, a bit line connected to the first dopant region and intersecting the word line, a bit line contact connecting the bit line to the first dopant region, a landing pad on the second dopant region, and a storage node contact connecting the landing pad to the second dopant region, the storage node contact including a first portion in contact with the second dopant region, the first portion including a single-crystal silicon, and a second portion on the first portion and including a poly-silicon.