公开(公告)号：US20240324185A1

公开(公告)日：2024-09-26

申请号：US18611395

申请日：2024-03-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seokjae WON ,  Yoongoo KANG ,  Jaehong PARK

IPC: H10B12/00

CPC classification number: H10B12/482 ,  H10B12/315 ,  H10B12/485

Abstract: The present disclosure provides semiconductor devices including a bit line. In some embodiments, a semiconductor device includes a substrate including a plurality of active regions defined by device isolation layers, a plurality of bit lines extending in a first horizontal direction on the substrate, a bit line contact between a first active region of the plurality of active regions and a first bit line of the plurality of bit lines on the first active region, and an active pad on a second active region of the plurality of active regions adjacent to the first active region. The bit line contact includes a first contact layer and a second contact layer on the first contact layer. The active pad is disposed to face the bit line contact.

公开(公告)号：US20250024667A1

公开(公告)日：2025-01-16

申请号：US18771723

申请日：2024-07-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yoongoo KANG ,  Hyunjung LEE ,  Jaehong PARK

IPC: H10B12/00

Abstract: Provided is a semiconductor device including a peripheral circuit structure including peripheral circuit transistors, bit lines on the peripheral circuit structure and extending in a first horizontal direction, back gate lines extending in a second horizontal direction at a vertical level higher than the bit lines, word lines extending in the second horizontal direction at a vertical level higher than the bit lines and alternating with the back gate lines, a plurality of vertical channel layers in a matrix form on the bit lines, each of the vertical channel layers including a first sidewall extending in a vertical direction and facing a corresponding back gate line, a second sidewall opposite to the first sidewall and facing a corresponding word line, a part of the second sidewall adjacent to a bit line having a curved shape, contact pads on the vertical channel layers, and storage nodes on the contact pads.

公开(公告)号：US20220093387A1

公开(公告)日：2022-03-24

申请号：US17222195

申请日：2021-04-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dain LEE ,  Yoongoo KANG ,  Wonseok YOO ,  Jinwon MA ,  Kyungwook PARK ,  Changwoo SEO ,  Suyoun SONG

IPC: H01L21/02 ,  C23C16/455

Abstract: A semiconductor device manufacturing method includes loading a semiconductor substrate into a chamber, the semiconductor substrate including a silicon oxide film, depositing a seed layer on the silicon oxide film by supplying a first silicon source material, supplying a purge gas on the seed layer, depositing a protective layer on the seed layer by repeating a first cycle, the first cycle including supplying a base source material layer and subsequently supplying the first silicon source material, and depositing a silicon nitride film on the protective layer by repeating a second cycle, the second cycle including supplying a second silicon source material and subsequently supplying a nitrogen source material.

公开(公告)号：US20250048619A1

公开(公告)日：2025-02-06

申请号：US18421113

申请日：2024-01-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yoongoo KANG ,  Dongyoung KIM ,  Jaehong PARK ,  Seokjae WON

IPC: H10B12/00 ,  H01L23/528

Abstract: The present inventive concepts relate to semiconductor devices and methods for fabricating the same, and a semiconductor device according to some example embodiments includes: a substrate including an active region defined by a device isolation layer; a word line that crosses and overlaps the active region; a bit line crossing the active region in a direction different from the word line; a direct contact that connects the active region and the bit line and includes a metallic material; a buried contact connected to the active region; and a bit line spacer between the bit line and the buried contact, wherein a width of the direct contact is different from that of the bit line, and the bit line spacer is on an upper surface of the direct contact.

公开(公告)号：US20140120685A1

公开(公告)日：2014-05-01

申请号：US13791870

申请日：2013-03-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seong Hoon JEONG ,  Yoongoo KANG ,  Ho-Kyun AN ,  KONGSOO LEE ,  JAEJONG HAN

IPC: H01L45/00

CPC classification number: H01L27/2409 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/144

Abstract: A semiconductor device and method of forming a semiconductor device is disclosed. The method includes forming a first ion-implanted layer having an amorphous state in a substrate; forming an impurity region of a first conductive type in the substrate; forming a semiconductor pattern on the substrate; forming a first doped region of the first conductive type in the semiconductor pattern; and forming a second doped region of a second conductive type contrary to the first conductive type in the semiconductor pattern. The first ion-implanted layer is formed by implanting carbons ions or germanium ions in the substrate.

Abstract translation: 公开了一种形成半导体器件的半导体器件和方法。 该方法包括在基板中形成具有非晶状态的第一离子注入层; 在衬底中形成第一导电类型的杂质区; 在所述基板上形成半导体图案; 在半导体图案中形成第一导电类型的第一掺杂区域; 以及形成与所述半导体图案中的所述第一导电类型相反的第二导电类型的第二掺杂区域。 第一离子注入层通过在基底中注入碳离子或锗离子而形成。

公开(公告)号：US20220246620A1

公开(公告)日：2022-08-04

申请号：US17723218

申请日：2022-04-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yoongoo KANG ,  Wonseok YOO ,  Hokyun AN ,  Kyungwook PARK ,  Dain LEE

IPC: H01L27/108 ,  G11C5/06 ,  H01L29/06

Abstract: A DRAM device includes an isolation region defining source and drain regions in a substrate, a first bit line structure connected to the source region, a second bit line structure disposed on the isolation region, an inner spacer vertically extending on a first sidewall of the first bit line structure, an air gap is between the inner spacer and an outer spacer, a storage contact between the first and second bit line structures and connected to the drain region, a landing pad structure vertically on the storage contact, and a storage structure vertically on the landing pad structure. The sealing layer seals a top of the first air gap. The sealing layer includes a first sealing layer on a first sidewall of a pad isolation trench, and a second sealing layer on a second sidewall of the pad isolation trench and separated from the first sealing layer.

公开(公告)号：US20210066304A1

公开(公告)日：2021-03-04

申请号：US16837274

申请日：2020-04-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yoongoo KANG ,  Wonseok YOO ,  Hokyun AN ,  Kyungwook PARK ,  Dain LEE

IPC: H01L27/108 ,  G11C5/06 ,  H01L29/06

Abstract: A DRAM device includes an isolation region defining source and drain regions in a substrate, a first bit line structure connected to the source region, a second bit line structure disposed on the isolation region, an inner spacer vertically extending on a first sidewall of the first bit line structure, an air gap is between the inner spacer and an outer spacer, a storage contact between the first and second bit line structures and connected to the drain region, a landing pad structure vertically on the storage contact, and a storage structure vertically on the landing pad structure. The sealing layer seals a top of the first air gap. The sealing layer includes a first sealing layer on a first sidewall of a pad isolation trench, and a second sealing layer on a second sidewall of the pad isolation trench and separated from the first sealing layer.