知搜-全球专利检索

  1. Login
  2. Sign Up

Search Results

21 records (took 0.016 seconds)

    INTEGRATED CIRCUIT DEVICES HAVING BURIED WORD LINES THEREIN AND METHODS OF FORMING THE SAME
    1.
    发明公开
    INTEGRATED CIRCUIT DEVICES HAVING BURIED WORD LINES THEREIN AND METHODS OF FORMING THE SAME 审中-公开

    公开(公告)号：US20240114676A1

    公开(公告)日：2024-04-04

    申请号：US18525187

    申请日：2023-11-30

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Taejin PARK ,  Taehoon KIM ,  Kyujin KIM ,  Chulkwon PARK ,  Sunghee HAN ,  Yoosang HWANG

    IPC: H10B12/00

    CPC classification number: H10B12/34 ,  H10B12/053 ,  H10B12/315 ,  H10B12/482

    Abstract: An integrated circuit device includes a substrate having an active region and a word line trench therein. The word line trench includes a lower portion having a first width, and an upper portion, which extends between the lower portion and a surface of the substrate and has a second width that is greater than the first width. A word line is provided, which extends in and adjacent a bottom of the word line trench. A gate insulation layer is provided, which extends between the word line and sidewalls of the lower portion of the word line trench. An electrically insulating gate capping layer is provided in the upper portion of the word line trench. An insulation liner is provided, which extends between the gate capping layer and sidewalls of the upper portion of the word line trench. The gate insulation layer extends between the insulation liner and a portion of the gate capping layer, which extends within the upper portion of the word line trench.

    SEMICONDUCTOR DEVICE
    3.
    发明公开
    SEMICONDUCTOR DEVICE 审中-公开

    公开(公告)号：US20240290868A1

    公开(公告)日：2024-08-29

    申请号：US18404607

    申请日：2024-01-04

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Taejin PARK ,  Bongsoo KIM ,  Huijung KIM

    IPC: H01L29/66 ,  H01L29/06 ,  H10B12/00

    CPC classification number: H01L29/6656 ,  H01L29/0649 ,  H10B12/315

    Abstract: A semiconductor device includes a first structure including a first impurity region, a second impurity region, and an isolation region, a second structure on the first structure and including a contact opening penetrating through the second structure and exposing the first impurity region, a pattern structure including a contact portion connected to the first impurity region in the contact opening, and a line portion on the contact portion and the second structure, and a spacer structure between a side surface of the contact opening and the contact portion. The spacer structure includes a first spacer layer on the side surface of the contact opening, and a second spacer layer between the first spacer layer and the contact portion. A lower end of the second spacer layer is at a higher level than a lower surface of the contact portion.

    SEMICONDUCTOR MEMORY DEVICE AND METHOD OF FABRICATING THE SAME
    4.
    发明公开
    SEMICONDUCTOR MEMORY DEVICE AND METHOD OF FABRICATING THE SAME 审中-公开

    公开(公告)号：US20240365531A1

    公开(公告)日：2024-10-31

    申请号：US18768714

    申请日：2024-07-10

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Taejin PARK ,  Hui-Jung KIM ,  Sangho LEE

    IPC: H10B12/00

    CPC classification number: H10B12/315 ,  H10B12/0335 ,  H10B12/053 ,  H10B12/34 ,  H10B12/482

    Abstract: A semiconductor memory device includes active regions including first impurity regions and second impurity regions, word lines on the active regions and extended in a first direction, bit lines on the word lines and extended in a second direction crossing the first direction, the bit lines being connected to the first impurity regions, first contact plugs between the bit lines, the first contact plugs being connected to the second impurity regions, landing pads on the first contact plugs, respectively, and gap-fill structures filling spaces between the landing pads, top surfaces of the gap-fill structures being higher than top surfaces of the landing pads.

    SEMICONDUCTOR MEMORY DEVICES
    6.
    发明申请
    SEMICONDUCTOR MEMORY DEVICES 有权

    公开(公告)号：US20220189968A1

    公开(公告)日：2022-06-16

    申请号：US17373539

    申请日：2021-07-12

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Taejin PARK ,  Kyujin KIM ,  Chulkwon PARK ,  Sunghee HAN

    IPC: H01L27/108

    Abstract: A semiconductor memory device includes a substrate comprising a memory cell region and a dummy cell region surrounding the memory cell region, the memory cell region including a plurality of memory cells, a plurality of active regions in the memory cell region, each of the plurality of active regions extending in a long axis direction, the long axis direction being a diagonal direction with respect to a first horizontal direction and a second horizontal direction orthogonal to the first horizontal direction, each of the plurality of active regions having a first width in a short axis direction orthogonal to the long axis direction, and a plurality of dummy active regions in the dummy cell region, each extending in the long axis direction, each of the plurality of dummy active regions having a second width greater than the first width in the short axis direction.

    SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME
    9.
    发明公开
    SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME 审中-公开

    公开(公告)号：US20240341089A1

    公开(公告)日：2024-10-10

    申请号：US18474699

    申请日：2023-09-26

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Hosang LEE ,  Taejin PARK ,  Hyunjin LEE ,  Heejae CHAE ,  Yun CHOI

    IPC: H10B12/00

    CPC classification number: H10B12/485 ,  H10B12/02 ,  H10B12/482

    Abstract: A semiconductor device according to some example embodiments includes: a substrate that includes an active region between element isolation layers; a word line that overlaps the active region and extends in a first direction; a bit line that overlaps the active region and extends in a second direction crossing the first direction; a buried contact connected to the active region; a first pad between and connecting the active region and the bit line; a second pad between and connecting the active region and the buried contact; and a landing pad connected to the buried contact. Each of the element isolation layers includes a first element isolation layer and a second element isolation layer inside the first element isolation layer, and each of the first pad and the second pad are between the element isolation layers.

    SEMICONDUCTOR DEVICES
    10.
    发明公开
    SEMICONDUCTOR DEVICES 审中-公开

    公开(公告)号：US20240315010A1

    公开(公告)日：2024-09-19

    申请号：US18435198

    申请日：2024-02-07

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Taejin PARK ,  Jongmin KIM ,  Huijung KIM ,  Kiseok LEE ,  Myeongdong LEE

    IPC: H10B12/00

    CPC classification number: H10B12/34 ,  H10B12/03 ,  H10B12/482 ,  H10B12/488

    Abstract: Provided is a semiconductor device comprising: an active region defined by an element isolation film in a substrate; a word line extending in a first horizontal direction in the substrate; a bit line extending in a second horizontal direction crossing the first horizontal direction on the substrate; an additional pad disposed on the active region; and a buried contact on the additional pad wherein the buried contact is electrically connected to the active region by the additional pad, wherein the additional pad comprises a first surface that overlaps the word line in a vertical direction, and a second surface that is free of overlap with the word line in the vertical direction, and wherein, the first surface meets the second surface at a cusp.

Patent Agency Ranking