公开(公告)号：US20190139984A1

公开(公告)日：2019-05-09

申请号：US16220836

申请日：2018-12-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jongwon KIM ,  Keejeong Rho ,  Jin-Yeon Won ,  Tae-Wan Lim ,  Woohyun Park

IPC: H01L27/11582 ,  H01L27/11565

CPC classification number: H01L27/11582 ,  H01L27/11565

Abstract: Semiconductor memory devices and methods for manufacturing the same are provided. The device may include vertical channel structures that are two-dimensionally arranged on a substrate and vertically extend from the substrate. The device may also include bit lines on the vertical channel structures, and each of the bit lines may be commonly connected to the vertical channel structures arranged in a first direction. The device may further include common source lines that extend between the vertical channel structures in a second direction intersecting the first direction and a source strapping line that is disposed at the same vertical level as the bit lines and electrically connects the common source lines to each other.

公开(公告)号：US11925015B2

公开(公告)日：2024-03-05

申请号：US17024987

申请日：2020-09-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sang-Yong Park ,  Kee-Jeong Rho ,  Hyeong Park ,  Tae-Wan Lim

IPC: H10B12/00 ,  H01L23/31 ,  H01L23/528 ,  H01L29/423 ,  H01L29/78 ,  H01L29/792 ,  H10B43/27 ,  H10B43/30 ,  H10B43/35 ,  H10B43/40 ,  H10B43/50

CPC classification number: H10B12/50 ,  H01L23/3171 ,  H01L23/3185 ,  H01L23/528 ,  H01L29/42352 ,  H01L29/4236 ,  H01L29/7827 ,  H01L29/7926 ,  H10B43/27 ,  H10B43/30 ,  H10B43/35 ,  H10B43/40 ,  H10B43/50 ,  H01L2924/0002 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Vertical memory devices, and methods of manufacturing the same, include providing a substrate including a cell array region and a peripheral circuit region, forming a mold structure in the cell array region, forming an opening for a common source line passing through the mold structure and extending in a first direction perpendicular to a top surface of the substrate, forming a first contact plug having an inner sidewall delimiting a recessed region in the opening for the common source line, and forming a common source bit line contact electrically connected to the inner sidewall of the first contact plug.

公开(公告)号：US10608091B2

公开(公告)日：2020-03-31

申请号：US16121020

申请日：2018-09-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Tae-Wan Lim ,  Hojong Kang ,  Joowon Park

IPC: H01L23/52 ,  H01L29/423 ,  H01L23/31 ,  H01L27/11582 ,  H01L21/28 ,  H01L23/485 ,  H01L23/522 ,  H01L27/1157 ,  H01L27/11575 ,  H01L21/768 ,  H01L29/66 ,  H01L29/792

Abstract: A method for manufacturing a semiconductor device includes forming a conductive pattern on a substrate, forming a filling insulation layer covering the conductive pattern, forming a contact hole in the filling insulation layer and adjacent to the conductive pattern, forming an opening in the conductive pattern by removing a portion of the conductive pattern adjacent to the contact hole such that the opening is connected to the contact hole, and forming a contact plug filling the contact hole and the opening. A width of the opening is greater than a width of the contact hole.

公开(公告)号：US10700088B2

公开(公告)日：2020-06-30

申请号：US16220836

申请日：2018-12-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jongwon Kim ,  Keejeong Rho ,  Jin-Yeon Won ,  Tae-Wan Lim ,  Woohyun Park

IPC: H01L27/11582 ,  H01L27/11565

Abstract: Semiconductor memory devices and methods for manufacturing the same are provided. The device may include vertical channel structures that are two-dimensionally arranged on a substrate and vertically extend from the substrate. The device may also include bit lines on the vertical channel structures, and each of the bit lines may be commonly connected to the vertical channel structures arranged in a first direction. The device may further include common source lines that extend between the vertical channel structures in a second direction intersecting the first direction and a source strapping line that is disposed at the same vertical level as the bit lines and electrically connects the common source lines to each other.