公开(公告)号：US10559571B2

公开(公告)日：2020-02-11

申请号：US15952350

申请日：2018-04-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Eunjung Kim ,  Daeik Kim ,  Bong-Soo Kim ,  Jemin Park ,  Semyeong Jang ,  Yoosang Hwang

IPC: H01L21/02 ,  H01L27/108 ,  H01L21/768 ,  B08B7/00

Abstract: A method of fabricating a semiconductor memory device includes forming a bit line and a bit line capping pattern on the semiconductor substrate, forming a first spacer covering a sidewall of the bit line capping pattern and a sidewall of the bit line, forming a contact plug in contact with a sidewall of the first spacer and having a top surface that is lower than an upper end of the first spacer, removing an upper portion of the first spacer, forming a first sacrificial layer closing at least an entrance of the void, forming a second spacer covering the sidewall of the bit line capping pattern and having a bottom surface in contact with a top surface of the first spacer, and removing the first sacrificial layer. The bit line capping pattern is on the bit line. The contact plug includes a void exposed on the top surface.

公开(公告)号：US10373960B2

公开(公告)日：2019-08-06

申请号：US15845141

申请日：2017-12-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Daeik Kim ,  Semyeong Jang ,  Jemin Park ,  Yoosang Hwang

IPC: H01L21/28 ,  H01L21/71 ,  H01L27/108 ,  H01L29/792 ,  H01L21/8234

Abstract: A volatile memory device can include a bit line structure having a vertical side wall. A lower spacer can be on a lower portion of the vertical side wall, where the lower spacer can be defined by a first thickness from the vertical side wall to an outer side wall of the lower spacer. An upper spacer can be on an upper portion of the vertical side wall above the lower portion, where the upper spacer can be defined by a second thickness that is less than the first thickness, the upper spacer exposing an uppermost portion of the outer side wall of the lower spacer.

公开(公告)号：US10121793B2

公开(公告)日：2018-11-06

申请号：US15083819

申请日：2016-03-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyung-Eun Kim ,  Yongkwan Kim ,  Semyeong Jang ,  Jaehyoung Choi ,  Yoosang Hwang ,  Bong-Soo Kim

IPC: H01L27/108

Abstract: A semiconductor device includes storage electrodes on a substrate and one or more supporters configured to couple one or more portions of the storage electrodes. The semiconductor device may include multiple non-intersecting supporters extending in parallel to a surface of the substrate. At least one supporter may have an upper surface that is substantially coplanar with upper surfaces of the storage electrodes. The storage electrodes may include a capacitor dielectric layer that conformally covers one or more surfaces of the storage electrodes and one or more supporters. A storage electrode may include upper and lower storage electrodes coupled together. The upper and lower storage electrodes may have different horizontal widths.

公开(公告)号：US11088148B2

公开(公告)日：2021-08-10

申请号：US16509820

申请日：2019-07-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Daeik Kim ,  Semyeong Jang ,  Jemin Park ,  Yoosang Hwang

IPC: H01L27/108 ,  H01L21/28 ,  H01L29/792 ,  H01L21/71 ,  H01L21/8234

Abstract: A volatile memory device can include a bit line structure having a vertical side wall. A lower spacer can be on a lower portion of the vertical side wall, where the lower spacer can be defined by a first thickness from the vertical side wall to an outer side wall of the lower spacer. An upper spacer can be on an upper portion of the vertical side wall above the lower portion, where the upper spacer can be defined by a second thickness that is less than the first thickness, the upper spacer exposing an uppermost portion of the outer side wall of the lower spacer.

公开(公告)号：US10943812B2

公开(公告)日：2021-03-09

申请号：US16535808

申请日：2019-08-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Semyeong Jang ,  Bong-Soo Kim ,  Heejae Chae

IPC: H01L27/105 ,  H01L27/24 ,  H01L27/22 ,  H01L27/108 ,  H01L21/762

Abstract: A semiconductor device includes a first trench on the device region, a first device isolation layer in the first trench and defining an active pattern of the device region, a second trench on the interface region, and a second device isolation layer in the second trench. The second isolation layer includes a buried dielectric pattern, a dielectric liner pattern on the buried dielectric pattern, and a first gap-fill dielectric pattern on the dielectric liner pattern. The buried dielectric pattern includes a floor segment on a floor of the second trench, and a sidewall segment on a sidewall of the second trench. The sidewall segment has a thickness different from a thickness of the floor segment.

公开(公告)号：US20180286870A1

公开(公告)日：2018-10-04

申请号：US15845141

申请日：2017-12-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Daeik Kim ,  Semyeong Jang ,  Jemin Park ,  Yoosang Hwang

IPC: H01L27/108 ,  H01L29/792 ,  H01L21/28 ,  H01L21/71

CPC classification number: H01L27/10885 ,  H01L21/28273 ,  H01L21/71 ,  H01L21/823475 ,  H01L27/10808 ,  H01L27/10814 ,  H01L27/10823 ,  H01L27/10876 ,  H01L27/10882 ,  H01L29/40114 ,  H01L29/7926

Abstract: A volatile memory device can include a bit line structure having a vertical side wall. A lower spacer can be on a lower portion of the vertical side wall, where the lower spacer can be defined by a first thickness from the vertical side wall to an outer side wall of the lower spacer. An upper spacer can be on an upper portion of the vertical side wall above the lower portion, where the upper spacer can be defined by a second thickness that is less than the first thickness, the upper spacer exposing an uppermost portion of the outer side wall of the lower spacer.

公开(公告)号：US11744063B2

公开(公告)日：2023-08-29

申请号：US17374624

申请日：2021-07-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Daeik Kim ,  Semyeong Jang ,  Jemin Park ,  Yoosang Hwang

IPC: H01L21/71 ,  H01L21/28 ,  H01L29/792 ,  H01L21/8234 ,  H10B12/00

CPC classification number: H10B12/482 ,  H01L21/71 ,  H01L29/40114 ,  H01L29/7926 ,  H10B12/053 ,  H10B12/31 ,  H10B12/315 ,  H10B12/34 ,  H10B12/48 ,  H01L21/823475

Abstract: A volatile memory device can include a bit line structure having a vertical side wall. A lower spacer can be on a lower portion of the vertical side wall, where the lower spacer can be defined by a first thickness from the vertical side wall to an outer side wall of the lower spacer. An upper spacer can be on an upper portion of the vertical side wall above the lower portion, where the upper spacer can be defined by a second thickness that is less than the first thickness, the upper spacer exposing an uppermost portion of the outer side wall of the lower spacer.

公开(公告)号：US20210343724A1

公开(公告)日：2021-11-04

申请号：US17374624

申请日：2021-07-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Daeik Kim ,  Semyeong Jang ,  Jemin Park ,  Yoosang Hwang

IPC: H01L27/108 ,  H01L29/792 ,  H01L21/71 ,  H01L21/28

Abstract: A volatile memory device can include a bit line structure having a vertical side wall. A lower spacer can be on a lower portion of the vertical side wall, where the lower spacer can be defined by a first thickness from the vertical side wall to an outer side wall of the lower spacer. An upper spacer can be on an upper portion of the vertical side wall above the lower portion, where the upper spacer can be defined by a second thickness that is less than the first thickness, the upper spacer exposing an uppermost portion of the outer side wall of the lower spacer.

公开(公告)号：US09847278B2

公开(公告)日：2017-12-19

申请号：US15095327

申请日：2016-04-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyung-Eun Kim ,  Yongkwan Kim ,  Semyeong Jang ,  Jaehyoung Choi ,  Yoosang Hwang ,  Bong-Soo Kim

IPC: H01L21/70 ,  H01L21/76 ,  H01L23/482 ,  H01L29/06 ,  H01L21/762 ,  H01L21/768 ,  H01L27/108 ,  H01L23/522 ,  H01L23/532

CPC classification number: H01L23/4821 ,  H01L21/76264 ,  H01L21/7682 ,  H01L21/76897 ,  H01L23/5222 ,  H01L23/53295 ,  H01L27/10814 ,  H01L27/10855 ,  H01L27/10885 ,  H01L29/0649

Abstract: A semiconductor device includes first and second bit line structures on a substrate and spaced apart from each other, a via plug partially filling between the first and second bit line structures, a via pad in contact with an upper surface of the via plug and an upper sidewall of the first bit line structure, the via pad being spaced apart from an upper portion of the second bit line structure, a first cavity filled with air being between the via plug and the first bit line structure and a second cavity filled with air between the via plug and the second bit line structure, A gap capping spacer having a first portion on the upper sidewall of the first bit line structure and a second portion covers the first air spacer. A horizontal width of the first portion is smaller than that of the second portion.

公开(公告)号：US09287300B2

公开(公告)日：2016-03-15

申请号：US14569980

申请日：2014-12-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Eunjung Kim ,  Yong Kwan Kim ,  Jemin Park ,  Semyeong Jang ,  Sangyeon Han ,  Yoosang Hwang

IPC: H01L21/311 ,  H01L29/06 ,  H01L27/12 ,  H01L21/768

CPC classification number: H01L27/1288 ,  H01L21/7688 ,  H01L27/10814 ,  H01L27/10891

Abstract: The present inventive concepts provide methods for fabricating semiconductor devices. The method may comprise providing a substrate, stacking a conductive layer and a lower mask layer on the substrate, forming a plurality of hardmask layers each having an island shape on the lower mask layer, forming a plurality of upper mask patterns having island shapes arranged to expose portions of the lower mask layer, etching the exposed portions of the lower mask layer to expose portions of the conductive layer, and etching the exposed portions of the conductive layer to form a plurality of contact holes each exposing a portion of the substrate.

Abstract translation: 本发明构思提供了制造半导体器件的方法。 该方法可以包括提供衬底，在衬底上堆叠导电层和下掩模层，在下掩模层上形成各自具有岛状的多个硬掩模层，形成具有岛形的多个上掩模图案，其布置成 暴露下掩模层的部分，蚀刻下掩模层的暴露部分以暴露导电层的部分，并且蚀刻导电层的暴露部分以形成多个接触孔，每个接触孔暴露衬底的一部分。