公开(公告)号：US08859371B2

公开(公告)日：2014-10-14

申请号：US13795839

申请日：2013-03-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Myung Geun Song ,  Ki-Hyung Ko ,  Hayoung Jeon ,  Boun Yoon ,  Jeongnam Han

IPC: H01L21/8234

CPC classification number: H01L29/401 ,  H01L21/823462 ,  H01L29/66545

Abstract: Methods for manufacturing a semiconductor device having a dual gate dielectric layer may include providing a substrate including first and second regions, forming a first gate dielectric layer having a first thickness on the substrate, forming an interlayer insulating layer including first and second trenches exposing the first gate dielectric layer in the first and second regions, forming a sacrificial layer on the interlayer insulating layer and bottoms of the first and second trenches, forming a sacrificial pattern exposing the first gate dielectric layer of the bottom of the first trench, removing the first gate dielectric layer of the bottom of the first trench, forming a second gate dielectric layer having a second thickness on the bottom of the first trench, removing the sacrificial pattern, and forming a gate electrode on each of the first and second gate dielectric layers.

Abstract translation: 制造具有双栅极电介质层的半导体器件的方法可以包括提供包括第一和第二区域的衬底，在衬底上形成具有第一厚度的第一栅极电介质层，形成包括第一和第二沟槽的层间绝缘层， 在所述第一和第二区域中的栅介质层，在所述层间绝缘层和所述第一沟槽和所述第二沟槽的底部上形成牺牲层，形成暴露所述第一沟槽的底部的第一栅极介电层的牺牲图案，去除所述第一栅极 在所述第一沟槽的底部形成介电层，在所述第一沟槽的底部形成具有第二厚度的第二栅极介电层，去除所述牺牲图案，以及在所述第一和第二栅极电介质层中的每一个上形成栅电极。

公开(公告)号：US09984921B2

公开(公告)日：2018-05-29

申请号：US15802724

申请日：2017-11-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sang Hoon Ahn ,  Jong Min Baek ,  Myung Geun Song ,  Woo Kyung You ,  Byung Kwon Cho ,  Byung Hee Kim ,  Na Ein Lee

IPC: H01L21/00 ,  H01L21/768 ,  H01L21/311 ,  H01L21/3205 ,  H01L23/528

CPC classification number: H01L21/7682 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/32053 ,  H01L21/76834 ,  H01L21/76843 ,  H01L21/76849 ,  H01L21/7685 ,  H01L21/76856 ,  H01L21/76883 ,  H01L23/5222 ,  H01L23/528 ,  H01L23/53295

Abstract: A method of manufacturing a semiconductor device includes forming grooves in a first dielectric layer on a substrate, the first dielectric layer including a first part between the grooves, forming a first barrier layer and an interconnect layer in each groove, recessing the interconnect layer and the first barrier layer, forming a capping pattern on the recessed interconnect layer, etching at least a portion of the first part by a first etching process, sequentially etching the capping pattern and the at least a portion of the IMD part by a second etching process to form a trench, conformally forming a second barrier layer in the trench and on the recessed interconnection layer, and forming a second dielectric layer on the second barrier layer not to fill the trench such that an air gap is formed in the trench.

公开(公告)号：US09812353B2

公开(公告)日：2017-11-07

申请号：US15353984

申请日：2016-11-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sang Hoon Ahn ,  Jong Min Baek ,  Myung Geun Song ,  Woo Kyung You ,  Byung Kwon Cho ,  Byung Hee Kim ,  Na Ein Lee

IPC: H01L21/00 ,  H01L21/768 ,  H01L21/311 ,  H01L21/3205 ,  H01L23/528

CPC classification number: H01L21/7682 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/32053 ,  H01L21/76834 ,  H01L21/76843 ,  H01L21/76849 ,  H01L21/7685 ,  H01L21/76856 ,  H01L21/76883 ,  H01L23/5222 ,  H01L23/528 ,  H01L23/53295

Abstract: A method of manufacturing a semiconductor device includes forming grooves in a first dielectric layer on a substrate, the first dielectric layer including a first part between the grooves, forming a first barrier layer and an interconnect layer in each groove, recessing the interconnect layer and the first barrier layer, forming a capping pattern on the recessed interconnect layer, etching at least a portion of the first part by a first etching process, sequentially etching the capping pattern and the at least a portion of the IMD part by a second etching process to form a trench, conformally forming a second barrier layer in the trench and on the recessed interconnection layer, and forming a second dielectric layer on the second barrier layer not to fill the trench such that an air gap is formed in the trench.

公开(公告)号：US10819368B2

公开(公告)日：2020-10-27

申请号：US16547770

申请日：2019-08-22

Applicant: SAMSUNG ELECTRONICS CO., LTD. ,  Seoul National University R&DB Foundation

Inventor： Myung Geun Song ,  Myung Joo Kang ,  Byeong Eon Lee ,  Myoung Su Cho ,  Young Jin Koh ,  Geon Woo Kim ,  Sang Yeon Kim ,  Hyun Seo ,  Dong Jun Woo ,  Jae Woong Choi

IPC: H03M7/30 ,  H03M7/00 ,  H03M7/42 ,  H03M5/00

Abstract: A method for compressing time series data includes: reading original data including time series data; measuring a unit of the original data; determining a threshold for determining a range allowing for a difference between compressed data and the original data; performing longest distance downsampling to preserve an abnormal point of the original data; storing a start point and an end point of the original data; performing drop-out on the longest distance downsampling result, wherein the drop-out is not performed for the start point and the end point; and if the number of values of the original data is smaller than α times the original data length, storing at least one of the values of the original data as a reference point, wherein α is a real number having a value between 0 and 1.

公开(公告)号：US20200220555A1

公开(公告)日：2020-07-09

申请号：US16547770

申请日：2019-08-22

Applicant: SAMSUNG ELECTRONICS CO., LTD. ,  Seoul National University R&DB Foundation

Inventor： Myung Geun Song ,  Myung Joo Kang ,  Byeong Eon Lee ,  Myoung Su Cho ,  Young Jin Koh ,  Geon Woo Kim ,  Sang Yeon Kim ,  Hyun Seo ,  Dong Jun Woo ,  Jae Woong Choi

IPC: H03M7/30

Abstract: A method for compressing time series data includes: reading original data including time series data; measuring a unit of the original data; determining a threshold for determining a range allowing for a difference between compressed data and the original data; performing longest distance downsampling to preserve an abnormal point of the original data; storing a start point and an end point of the original data; performing drop-out on the longest distance downsampling result, wherein the drop-out is not performed for the start point and the end point; and if the number of values of the original data is smaller than a times the original data length, storing at least one of the values of the original data as a reference point, wherein α is a real number having a value between 0 and 1.

公开(公告)号：US20130244414A1

公开(公告)日：2013-09-19

申请号：US13795839

申请日：2013-03-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Myung Geun Song ,  Ki-Hyung Ko ,  Hayoung Jeon ,  Boun Yoon ,  Jeongnam Han

IPC: H01L29/40

CPC classification number: H01L29/401 ,  H01L21/823462 ,  H01L29/66545

Abstract: Methods for manufacturing a semiconductor device having a dual gate dielectric layer may include providing a substrate including first and second regions, forming a first gate dielectric layer having a first thickness on the substrate, forming an interlayer insulating layer including first and second trenches exposing the first gate dielectric layer in the first and second regions, forming a sacrificial layer on the interlayer insulating layer and bottoms of the first and second trenches, forming a sacrificial pattern exposing the first gate dielectric layer of the bottom of the first trench, removing the first gate dielectric layer of the bottom of the first trench, forming a second gate dielectric layer having a second thickness on the bottom of the first trench, removing the sacrificial pattern, and forming a gate electrode on each of the first and second gate dielectric layers.

Abstract translation: 制造具有双栅极电介质层的半导体器件的方法可以包括提供包括第一和第二区域的衬底，在衬底上形成具有第一厚度的第一栅极电介质层，形成包括第一和第二沟槽的层间绝缘层， 在所述第一和第二区域中的栅介质层，在所述层间绝缘层和所述第一沟槽和所述第二沟槽的底部上形成牺牲层，形成暴露所述第一沟槽的底部的第一栅极电介质层的牺牲图案，去除所述第一栅极 在所述第一沟槽的底部形成介电层，在所述第一沟槽的底部形成具有第二厚度的第二栅极介电层，去除所述牺牲图案，以及在所述第一和第二栅极电介质层中的每一个上形成栅电极。