公开(公告)号：US11869884B2

公开(公告)日：2024-01-09

申请号：US17559152

申请日：2021-12-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jong-Kyu Ryu ,  Min-Su Kim ,  Yong-Geol Kim ,  Dae-Seong Lee

IPC: H01L27/00 ,  H01L27/02 ,  H01L23/552 ,  G03F1/36 ,  H01L27/118 ,  G06F30/398

CPC classification number: H01L27/0207 ,  G03F1/36 ,  G06F30/398 ,  H01L23/552 ,  H01L27/11807 ,  H01L2027/11874 ,  H01L2027/11881 ,  H01L2027/11892

Abstract: A semiconductor device is provided. The semiconductor device includes a first hard macro; a second hard macro spaced apart from the first hard macro in a first direction by a first distance; a head cell disposed in a standard cell area between the first hard macro and the second hard macro, the head cell being configured to perform power gating of a power supply voltage provided to one from among the first hard macro and the second hard macro; a plurality of first ending cells disposed in the standard cell area adjacent to the first hard macro; and a plurality of second ending cells disposed in the standard cell area adjacent to the second hard macro, the head cell not overlapping the plurality of first ending cells and the plurality of second ending cells.

公开(公告)号：US10545555B2

公开(公告)日：2020-01-28

申请号：US15261033

申请日：2016-09-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yun-Hui Han ,  Min-Su Kim ,  Chul-Woo Park ,  Seung-Chul Choi

IPC: G06F1/3206 ,  H02J7/00 ,  G05B15/02 ,  G06F1/3215 ,  G06F1/3234 ,  G06F1/3203

Abstract: An electronic device is provided. The electronic device includes a battery, a power management integrated circuit (PMIC), that is electrically connected to the battery, adjusts at least part of power received from the battery, and outputs a controlled power, a processor electrically connected to the PMIC, at least one power sensor that is one of electrically connected between the battery and the PMIC and constitutes a part of the PMIC, and a control circuit electrically connected to the at least one power sensor. The control circuit acquires at least one of a current value and a power value input into the PMIC from the battery, determines whether at least one of the acquired current value and power value is greater than or equal to a threshold, and generates a first signal for controlling at least one of the PMIC and the processor, at least partially based on the determination.

公开(公告)号：US10230373B2

公开(公告)日：2019-03-12

申请号：US15139949

申请日：2016-04-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ah-Reum Kim ,  Hyun Lee ,  Min-Su Kim

IPC: H03K3/356 ,  H03K19/0185 ,  H03K19/00 ,  H03K3/037 ,  H03K3/012

Abstract: Provided are semiconductor circuits. A semiconductor circuit includes: a first circuit configured to propagate a value of a first node to a second node based on a voltage level of a clock signal; a second circuit configured to propagate a value of the second node to a third node based on the voltage level of the clock signal; and a third circuit configured to determine a value of the third node based on a voltage level of the second node and the voltage level of the clock signal, wherein the first circuit comprises a first transistor gated to a voltage level of the first node, a second transistor connected in series with the first transistor and gated to the voltage level of the third node, and a third transistor connected in parallel with the first and second transistors and gated to a voltage level of the clock signal to provide the value of the first node to the second node.

公开(公告)号：US10177745B2

公开(公告)日：2019-01-08

申请号：US15247430

申请日：2016-08-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Min-Su Kim

IPC: H03K3/356 ,  H03K3/012 ,  G01R31/3185

Abstract: Provided is a semiconductor circuit which includes a first circuit configured to determine a voltage level of a feedback node based on a voltage level of input data, a voltage level of a latch input node, and a voltage level of a clock signal, a second circuit configured to pre-charge the latch input node based on the voltage level of the clock signal, a third circuit configured to pull down the latch input node based on the voltage level of the feedback node and the voltage level of the clock signal, a latch configured to output output data based on the voltage level of the clock signal and the voltage level of the latch input node, and a control circuit included in at least one of the first to third circuits and the latch and configured to receive the control signal.

公开(公告)号：US20180145661A1

公开(公告)日：2018-05-24

申请号：US15669072

申请日：2017-08-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyun-Chul HWANG ,  Min-Su Kim ,  Dae-Seong Lee

IPC: H03K3/012 ,  H03K3/356

CPC classification number: H03K3/012 ,  H03K3/356182 ,  H03K3/35625

Abstract: A flip-flop includes a first node charging circuit configured to charge a first node with inverted input data generated by inverting input data, a second node charging circuit configured to charge a second node with the input data, and first through eighth NMOS transistors. The flip-flop is configured to latch the input data at rising edges of a clock signal and output latched input data as output data. The flip-flop includes an internal circuit configured to charge a sixth node with inverted input data generated by inverting the latched input data.

公开(公告)号：US09899990B2

公开(公告)日：2018-02-20

申请号：US15253270

申请日：2016-08-31

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： San-Ha Kim ,  Min-Su Kim ,  Matthew Berzins

IPC: H03K3/356 ,  H03K3/012

CPC classification number: H03K3/012 ,  H03K3/356121

Abstract: A semiconductor circuit includes a first circuit and a second circuit. The first circuit determines a logic level of a second node and a logic level of a third node, on the basis of a logic level of input data, a logic level of a clock signal, and a logic level of a first node. The second circuit determines the logic level of the first node, on the basis of the logic level of the clock signal, the logic level of the second node and the logic level of the third node. The first circuit comprises a sub-circuit and a first transistor. The first circuit determines the logic level of the second node, on the basis of the logic level of the input data and the logic level of the first node. The first transistor is gated to the logic level of the clock signal to connect the third node with the second node.

公开(公告)号：US09891283B2

公开(公告)日：2018-02-13

申请号：US15281998

申请日：2016-09-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Min-Su Kim ,  Matthew Berzins ,  Jong-Woo Kim

IPC: G01R31/3177 ,  H03K19/21 ,  H03K3/037 ,  G01R31/3185 ,  H03K3/3562 ,  G01R31/317

CPC classification number: G01R31/3177 ,  G01R31/31723 ,  G01R31/31727 ,  G01R31/318541 ,  H03K3/0372 ,  H03K3/35625 ,  H03K19/21

Abstract: A multi-bit flip-flop includes a plurality of multi-bit flip-flop blocks that share a clock signal. Each of the multi-bit flip-flop blocks includes a single inverter and a plurality of flip-flops. The single inverter generates an inverted clock signal by inverting the clock signal. Each of the flip-flops includes a master latch part and a slave latch part and operates the master latch part and the slave latch part based on the clock signal and the inverted clock signal. Here, the flip-flops are triggered at rising edges of the clock signal. Thus, the multi-bit flip-flop operating as a master-slave flip-flop may minimize (or, reduce) power consumption occurring in a clock path through which the clock signal is transmitted.

公开(公告)号：US20170063377A1

公开(公告)日：2017-03-02

申请号：US15248099

申请日：2016-08-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyun-Chul HWANG ,  Min-Su Kim

IPC: H03K19/0185 ,  H03K19/20

CPC classification number: H03K19/018521 ,  H03K3/012 ,  H03K3/037 ,  H03K3/356104 ,  H03K3/356121 ,  H03K3/356139 ,  H03K19/0013 ,  H03K19/0016 ,  H03K19/20

Abstract: A semiconductor circuit includes a first circuit and a second circuit. The first circuit is configured to generate a voltage level at a first node based on a voltage level of input data, an inverted value of the voltage level at the first node, a voltage level of a clock signal, and a voltage level at a second node; and the second circuit is configured to generate the voltage level at the second node based on the voltage level of input data, an inverted value of the voltage level at the second node, the voltage level of the clock signal, and the inverted value of the voltage level at the first node. When the clock signal is at a first level, the first and second nodes have different logical levels. When the clock signal is at a second level, the first and second nodes have the same logical level.

Abstract translation: 半导体电路包括第一电路和第二电路。 第一电路被配置为基于输入数据的电压电平，第一节点处的电压电平的反相值，时钟信号的电压电平和第二节点处的电压电平来在第一节点处产生电压电平 节点; 并且第二电路被配置为基于输入数据的电压电平，第二节点处的电压电平的反相值，时钟信号的电压电平和第二节点的反相值来生成第二节点处的电压电平 第一节点的电压电平。 当时钟信号处于第一级时，第一和第二节点具有不同的逻辑电平。 当时钟信号处于第二级时，第一和第二节点具有相同的逻辑电平。

公开(公告)号：US09473123B2

公开(公告)日：2016-10-18

申请号：US14645818

申请日：2015-03-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Min-Su Kim

IPC: H03K3/00 ,  H03K3/356 ,  G01R31/3185

CPC classification number: H03K3/012 ,  G01R31/318541 ,  H03K3/356104 ,  H03K3/356139

Abstract: Provided is a semiconductor circuit which includes a first circuit configured to determine a voltage level of a feedback node based on a voltage level of input data, a voltage level of a latch input node, and a voltage level of a clock signal, a second circuit configured to pre-charge the latch input node based on the voltage level of the clock signal, a third circuit configured to pull down the latch input node based on the voltage level of the feedback node and the voltage level of the clock signal, a latch configured to output output data based on the voltage level of the clock signal and the voltage level of the latch input node, and a control circuit included in at least one of the first to third circuits and the latch and configured to receive the control signal.

Abstract translation: 提供一种半导体电路，其包括：第一电路，被配置为基于输入数据的电压电平，锁存输入节点的电压电平和时钟信号的电压电平来确定反馈节点的电压电平;第二电路 配置为基于所述时钟信号的电压电平对所述锁存器输入节点进行预充电，第三电路被配置为基于所述反馈节点的电压电平和所述时钟信号的电压电平来下拉所述锁存器输入节点;锁存器 被配置为基于所述时钟信号的电压电平和所述锁存输入节点的电压电平输出输出数据，以及包括在所述第一至第三电路和所述锁存器中的至少一个中的控制电路，并且被配置为接收所述控制信号。

公开(公告)号：US09312857B2

公开(公告)日：2016-04-12

申请号：US14208053

申请日：2014-03-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Min-Su Kim ,  Jin-Seung Son ,  Prashant Kenkare

IPC: H03K19/0185 ,  H03K19/00 ,  H03K19/003

CPC classification number: H03K19/0185 ,  H03K19/0013 ,  H03K19/00361

Abstract: A semiconductor circuit includes: a first circuit configured to provide first voltage to an output node when a voltage level of an input node is at a first level; a second circuit configured to provide second voltage to the output node when the voltage level of the input node is at a second level; and a third circuit configured to provide third voltage to the output node when the second voltage is provided to the output node, where the second circuit is turned off when the third voltage is provided to the output node.

Abstract translation: 半导体电路包括：第一电路，被配置为当输入节点的电压电平处于第一电平时向输出节点提供第一电压; 第二电路，被配置为当输入节点的电压电平处于第二电平时，向输出节点提供第二电压; 以及第三电路，被配置为当所述第二电压被提供给所述输出节点时向所述输出节点提供第三电压，其中当所述第三电压被提供给所述输出节点时所述第二电路被关断。