公开(公告)号：US20170302279A1

公开(公告)日：2017-10-19

申请号：US15642887

申请日：2017-07-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyun-Chul HWANG ,  Min-Su KIM

IPC: H03K19/0185 ,  H03K19/00 ,  H03K3/356 ,  H03K3/037 ,  H03K19/20 ,  H03K3/012

CPC classification number: H03K19/018521 ,  H03K3/012 ,  H03K3/037 ,  H03K3/356104 ,  H03K3/356121 ,  H03K3/356139 ,  H03K19/0013 ,  H03K19/0016 ,  H03K19/20

Abstract: A semiconductor circuit includes a first circuit and a second circuit. The first circuit is configured to generate a voltage level at a first node based on a voltage level of input data, an inverted value of the voltage level at the first node, a voltage level of a clock signal, and a voltage level at a second node; and the second circuit is configured to generate the voltage level at the second node based on the voltage level of input data, an inverted value of the voltage level at the second node, the voltage level of the clock signal, and the inverted value of the voltage level at the first node. When the clock signal is at a first level, the first and second nodes have different logical levels. When the clock signal is at a second level, the first and second nodes have the same logical level.

公开(公告)号：US20170324413A1

公开(公告)日：2017-11-09

申请号：US15661153

申请日：2017-07-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyun-Chul HWANG ,  Min-Su KIM

IPC: H03K19/0185 ,  H03K19/20 ,  H03K3/037

CPC classification number: H03K19/018521 ,  H03K3/012 ,  H03K3/037 ,  H03K3/356121 ,  H03K19/20

Abstract: A semiconductor circuit includes a first circuit and a second circuit. The first circuit is configured to generate a voltage level at a first node based on a voltage level of input data, an inverted value of the voltage level at the first node, a voltage level of a clock signal, and a voltage level at a second node; and the second circuit is configured to generate the voltage level at the second node based on the voltage level of input data, an inverted value of the voltage level at the second node, the voltage level of the clock signal, and the inverted value of the voltage level at the first node. When the clock signal is at a first level, the first and second nodes have different logical levels. When the clock signal is at a second level, the first and second nodes have the same logical level.

公开(公告)号：US20190074825A1

公开(公告)日：2019-03-07

申请号：US15906693

申请日：2018-02-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyun-Chul HWANG ,  Jong-Kyu RYU ,  Min-Su KIM

IPC: H03K5/135 ,  H03K3/356 ,  H03K3/037

Abstract: A sequential circuit includes a first gate circuit, a second gate circuit and an output circuit. The first circuit generates a first signal based on an input signal, an input clock signal and a second signal. The second circuit generates an internal clock signal by performing a NOR operation on the first signal and an inversion clock signal which is inverted from the input clock signal, and generates the second signal based on the internal clock signal and the input signal. The output circuit generates an output signal based on the second signal. Operation speed of the sequential circuit and the integrated circuit including the same may be increased by increasing the negative setup time reflecting a transition of the input signal after a transition of the input clock signal, through mutual controls between the first circuit and the second circuit.

公开(公告)号：US20180145661A1

公开(公告)日：2018-05-24

申请号：US15669072

申请日：2017-08-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyun-Chul HWANG ,  Min-Su Kim ,  Dae-Seong Lee

IPC: H03K3/012 ,  H03K3/356

CPC classification number: H03K3/012 ,  H03K3/356182 ,  H03K3/35625

Abstract: A flip-flop includes a first node charging circuit configured to charge a first node with inverted input data generated by inverting input data, a second node charging circuit configured to charge a second node with the input data, and first through eighth NMOS transistors. The flip-flop is configured to latch the input data at rising edges of a clock signal and output latched input data as output data. The flip-flop includes an internal circuit configured to charge a sixth node with inverted input data generated by inverting the latched input data.

公开(公告)号：US20170063377A1

公开(公告)日：2017-03-02

申请号：US15248099

申请日：2016-08-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyun-Chul HWANG ,  Min-Su Kim

IPC: H03K19/0185 ,  H03K19/20

CPC classification number: H03K19/018521 ,  H03K3/012 ,  H03K3/037 ,  H03K3/356104 ,  H03K3/356121 ,  H03K3/356139 ,  H03K19/0013 ,  H03K19/0016 ,  H03K19/20

Abstract: A semiconductor circuit includes a first circuit and a second circuit. The first circuit is configured to generate a voltage level at a first node based on a voltage level of input data, an inverted value of the voltage level at the first node, a voltage level of a clock signal, and a voltage level at a second node; and the second circuit is configured to generate the voltage level at the second node based on the voltage level of input data, an inverted value of the voltage level at the second node, the voltage level of the clock signal, and the inverted value of the voltage level at the first node. When the clock signal is at a first level, the first and second nodes have different logical levels. When the clock signal is at a second level, the first and second nodes have the same logical level.

Abstract translation: 半导体电路包括第一电路和第二电路。 第一电路被配置为基于输入数据的电压电平，第一节点处的电压电平的反相值，时钟信号的电压电平和第二节点处的电压电平来在第一节点处产生电压电平 节点; 并且第二电路被配置为基于输入数据的电压电平，第二节点处的电压电平的反相值，时钟信号的电压电平和第二节点的反相值来生成第二节点处的电压电平 第一节点的电压电平。 当时钟信号处于第一级时，第一和第二节点具有不同的逻辑电平。 当时钟信号处于第二级时，第一和第二节点具有相同的逻辑电平。