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    Low-power low-setup integrated clock gating cell with complex enable selection
    1.
    发明授权
    Low-power low-setup integrated clock gating cell with complex enable selection 有权

    公开(公告)号：US10819342B2

    公开(公告)日：2020-10-27

    申请号：US16352816

    申请日：2019-03-13

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Matthew Berzins ,  Lalitkumar Motagi

    IPC: H03K19/00

    Abstract: A low-power low-setup integrated clock gating (ICG) cell is disclosed. The disclosed ICG cell includes a NOR gate configured to receive an enable (E) signal and a test enable (SE) signal, and to output an EN signal. The ICG cell may include a complex gate configured to receive the EN signal and a clock (CK) signal, and to output a latched enable (ELAT) signal. The ICG cell may further include a NAND gate configured to receive the ELAT signal and the CK signal, and to output an inverted enabled clock (ECKN) signal. The ICG cell may further include an inverter configured to receive the ECKN signal from the NAND gate, and to output an enable clock (ECK) signal.

    Layout connection isolation technique for improving immunity to jitter and voltage drop in a standard cell
    2.
    发明授权
    Layout connection isolation technique for improving immunity to jitter and voltage drop in a standard cell 有权

    公开(公告)号：US10607982B2

    公开(公告)日：2020-03-31

    申请号：US16150249

    申请日：2018-10-02

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Matthew Berzins ,  Charles A. Cornell

    IPC: H01L23/52 ,  H01L27/02 ,  H03K19/003 ,  H01L23/522 ,  H01L23/528

    Abstract: A standard cell architecture provides an improved immunity to power-supply voltage-drop, does not induce power-supply voltage drop on a continuous-row power rail of a standard cell, and maintains standard-cell environment compatibility. A circuit includes a first metal layer and a second metal layer that are formed different distances above a substrate. At least one first standard cell drives a first timing signal and includes at least one transistor receiving power from a first power rail in the first metal layer. At least one second standard cell drives a second timing signal and includes at least one transistor receiving power from a second power rail in the second metal layer. The second power rail has both a low peak noise level and a resistance that is lower than that of the first metal layer.

    Multi-bit flip-flops
    3.
    发明授权
    Multi-bit flip-flops 有权

    公开(公告)号：US10353000B2

    公开(公告)日：2019-07-16

    申请号：US15479310

    申请日：2017-04-05

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Doo-Seok Yoon ,  Min-Su Kim ,  Chung-Hee Kim ,  Dae-Seong Lee ,  Hyun Lee ,  Matthew Berzins ,  James Lim

    IPC: G01R31/3177 ,  H03K3/037 ,  G01R31/317

    Abstract: A multi-bit flip-flop includes: a single scan input pin to receive a scan input signal, a plurality of data input pins to receive first and second data input signals, a first scan flip-flop to select one of the scan input signal and the first data input signal as a first selection signal in response to a scan enable signal and to latch the first selection signal to provide a first output signal, a second scan flip-flop to select one of an internal signal corresponding to the first output signal and the second data input signal as a second selection signal in response to the scan enable signal and to latch the second selection signal to provide a second output signal, and a plurality of output pins to output the first and second output signals, wherein scan paths of the first and second scan flip-flops are connected to each other.

    System and method for improving scan hold-time violation and low voltage operation in sequential circuit
    4.
    发明授权
    System and method for improving scan hold-time violation and low voltage operation in sequential circuit 有权

    公开(公告)号：US10262723B2

    公开(公告)日：2019-04-16

    申请号：US15680198

    申请日：2017-08-17

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Matthew Berzins

    IPC: G11C11/00 ,  G11C11/417 ,  H03K3/037

    Abstract: According to one general aspect, an apparatus may include a flip-flop circuit. The flip-flop circuit may include a selection circuit, a memory element circuit, a clock circuit. The selection circuit to select, as the selected input signal, between at least two input signals. The memory element circuit synchronously controlled by a clock signal, and configured to store the selected input signal. The clock circuit configured to output, at least, an earlier version of the clock signal and a later version of the clock signal. The selection circuit is configured to be synchronously controlled, at least in part, by the earlier version of the clock signal such that the selected input signal is held stable when being read by the memory element circuit.

    System and method for improving scan hold-time violation and low voltage operation in sequential circuit
    6.
    发明授权
    System and method for improving scan hold-time violation and low voltage operation in sequential circuit 有权

    公开(公告)号：US10720204B2

    公开(公告)日：2020-07-21

    申请号：US16358681

    申请日：2019-03-19

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Matthew Berzins

    IPC: G11C11/00 ,  G11C11/417 ,  H03K3/037

    Abstract: According to one general aspect, an apparatus may include a flip-flop circuit. The flip-flop circuit may include a selection circuit, a memory element circuit, a clock circuit. The selection circuit to select, as the selected input signal, between at least two input signals. The memory element circuit synchronously controlled by a clock signal, and configured to store the selected input signal. The clock circuit configured to output, at least, an earlier version of the clock signal and a later version of the clock signal. The selection circuit is configured to be synchronously controlled, at least in part, by the earlier version of the clock signal such that the selected input signal is held stable when being read by the memory element circuit.

    Semiconductor circuit including flip-flop
    7.
    发明授权
    Semiconductor circuit including flip-flop 有权

    公开(公告)号：US09899990B2

    公开(公告)日：2018-02-20

    申请号：US15253270

    申请日：2016-08-31

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： San-Ha Kim ,  Min-Su Kim ,  Matthew Berzins

    IPC: H03K3/356 ,  H03K3/012

    CPC classification number: H03K3/012 ,  H03K3/356121

    Abstract: A semiconductor circuit includes a first circuit and a second circuit. The first circuit determines a logic level of a second node and a logic level of a third node, on the basis of a logic level of input data, a logic level of a clock signal, and a logic level of a first node. The second circuit determines the logic level of the first node, on the basis of the logic level of the clock signal, the logic level of the second node and the logic level of the third node. The first circuit comprises a sub-circuit and a first transistor. The first circuit determines the logic level of the second node, on the basis of the logic level of the input data and the logic level of the first node. The first transistor is gated to the logic level of the clock signal to connect the third node with the second node.

    Low power toggle latch-based flip-flop including integrated clock gating logic
    9.
    发明授权
    Low power toggle latch-based flip-flop including integrated clock gating logic 有权
    低功耗触发闩锁触发器，包括集成时钟门控逻辑

    公开(公告)号：US09419590B2

    公开(公告)日：2016-08-16

    申请号：US14267883

    申请日：2014-05-01

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Matthew Berzins ,  Christina Wells

    IPC: H03K3/012 ,  H03K3/037

    CPC classification number: H03K3/012 ,  H03K3/037 ,  H03K3/0372

    Abstract: Inventive aspects include integrated clock gating logic that can generate an internal glitch-free clock signal. Inventive aspects further include a toggle latch that is coupled to the integrated clock gating logic. The toggle latch can receive the internal clock signal from the integrated clock gating logic. The toggle latch can toggle and latch a data value responsive to the internal clock signal. The integrated clock gating logic can include a latch to latch a clock gating logic signal responsive to a clock signal. The clock gating logic signal can cause the internal clock signal to be quiescent when the input data to the flip-flop remains constant, thereby conserving power consumption.

    Abstract translation: 发明方面包括可产生内部无毛刺时钟信号的集成时钟门控逻辑。 发明方面还包括耦合到集成时钟选通逻辑的触发锁存器。 触发锁存器可以从集成时钟门控逻辑接收内部时钟信号。 触发锁存器可以响应于内部时钟信号切换并锁存数据值。 集成时钟门控逻辑可以包括锁存器，以响应于时钟信号锁存时钟门控逻辑信号。 当触发器的输入数据保持不变时，时钟选通逻辑信号可能导致内部时钟信号静止，从而节省功耗。

    Method for reducing power consumption in scannable flip-flops without additional circuitry
    10.
    发明授权
    Method for reducing power consumption in scannable flip-flops without additional circuitry 有权

    公开(公告)号：US11092649B2

    公开(公告)日：2021-08-17

    申请号：US16523993

    申请日：2019-07-26

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Matthew Berzins

    IPC: G01R31/28 ,  G01R31/3185 ,  G01R31/317

    Abstract: According to one general aspect, an apparatus may include a first power signal having a high voltage. The apparatus may include a second power signal having a low voltage. The apparatus may include a third power signal having a voltage configured to switch between the high voltage and the low voltage. The apparatus may include a latching circuit powered by the first power signal and the second power signal. The apparatus may include a selection circuit configured to select between, at least, a first data signal and a second data signal, and powered by the first power signal, the second power signal, and the third power signal.

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