公开(公告)号：US10950724B2

公开(公告)日：2021-03-16

申请号：US16364303

申请日：2019-03-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yeoncheol Heo ,  Sharma Deepak ,  Kwanyoung Chun

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/10 ,  H01L21/8238 ,  H01L27/02 ,  H01L29/786 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423

Abstract: A semiconductor device includes a substrate with an upper surface and a lower surface, and first to third active patterns extending from the upper surface of the substrate. The first to third active patterns are arranged adjacent to each other in a first direction. The second active pattern is disposed between the first and third active patterns. The semiconductor device also includes a first gate electrode surrounding side surfaces of the first and second active patterns, and a second gate electrode surrounding side surfaces of the third active pattern. Each of the first to third active patterns includes a first impurity region, a channel region, and a second impurity region.

公开(公告)号：US11640959B2

公开(公告)日：2023-05-02

申请号：US16931585

申请日：2020-07-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jungkyu Chae ,  Kwanyoung Chun ,  Yoonjin Kim

IPC: H01L27/00 ,  H01L27/02

Abstract: A semiconductor device includes a pair of first and second dummy active regions extending in a first horizontal direction and spaced apart from each other in a second horizontal direction; a pair of first and second circuit active regions extending in the first horizontal direction and spaced apart in the second horizontal direction; and a plurality of line patterns extending in the second horizontal direction and spaced apart in the first horizontal direction. The pair of first and second dummy active regions may be between a pair of line patterns adjacent to each other among the plurality of line patterns. At least one of the first and second dummy active regions may have a width-changing portion in which a width of the at least one of the first and second dummy active regions changes in the second horizontal direction between the pair of line patterns adjacent to each other.

公开(公告)号：US20230068716A1

公开(公告)日：2023-03-02

申请号：US17751093

申请日：2022-05-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Byungju Kang ,  Raheel Azmat ,  Jiwook Kwon ,  Suhyeon Kim ,  Kwanyoung Chun

IPC: H01L27/02 ,  G06F30/392 ,  G06F30/394 ,  H01L23/528 ,  H01L23/522 ,  H01L27/118

Abstract: A semiconductor device includes: a standard cell including a plurality of active patterns extending in a first direction, a gate structure intersecting the plurality of active patterns and extending in a second direction, and source/drain regions respectively provided on the plurality of active patterns positioned on both sides of the gate structure; a plurality of signal lines extending on the standard cell in the first direction, arranged in the second direction, and electrically connected to the standard cell; and first and second power straps extending on the standard cell in the first direction, electrically connected to some of the source/drain regions, and supplying power to the standard cell, wherein each of the first and second power straps is provided on the standard cell while provided on the same line as any one of the plurality of signal lines in the first direction.

公开(公告)号：US11348918B2

公开(公告)日：2022-05-31

申请号：US16864260

申请日：2020-05-01

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Taehyung Kim ,  Jinwoo Jeong ,  Jiwook Kwon ,  Raheel Azmat ,  Kwanyoung Chun

IPC: H01L27/092 ,  H01L23/528 ,  H01L27/11 ,  H01L29/06 ,  H01L29/423 ,  H01L29/78 ,  H01L29/786 ,  H01L21/02 ,  H01L21/8238 ,  H01L29/66 ,  H01L27/02

Abstract: A semiconductor device including a substrate; first to third active patterns on an upper portion of the substrate, the active patterns being sequentially arranged in a first direction and extending in a second direction crossing the first direction; first to third power rails respectively connected to the first to third active patterns, wherein a width of the second active pattern in the first direction is at least two times a width of the first active pattern in the first direction and is at least two times a width of the third active pattern in the first direction, the first active pattern is not vertically overlapped with the first power rail, the second active pattern is vertically overlapped with the second power rail, and the third active pattern is not vertically overlapped with the third power rail.

公开(公告)号：US09659871B2

公开(公告)日：2017-05-23

申请号：US14505788

申请日：2014-10-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Raheel Azmat ,  Rwik Sengupta ,  Chulhong Park ,  Kwanyoung Chun

IPC: H01L27/24 ,  H01L23/538 ,  H01L27/118 ,  H03K19/173 ,  H01L27/02

CPC classification number: H01L27/11807 ,  H01L23/535 ,  H01L23/5384 ,  H01L27/0207 ,  H01L29/0649 ,  H01L2924/0002 ,  H03K19/1736 ,  H01L2924/00

Abstract: Provided is a semiconductor device including a substrate with a plurality of logic cells, transistors provided in the plurality of logic cells, contact plugs connected to electrodes of the transistors, first via plugs in contact with top surfaces of the contact plugs, and first wires in contact with top surfaces of the first via plugs. The first wires may include a common conductive line connected to the plurality of logic cells through the contact plugs, and all of the first wires may be shaped like a straight line extending parallel to a specific direction.

公开(公告)号：US09640444B2

公开(公告)日：2017-05-02

申请号：US14807220

申请日：2015-07-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jung-Ho Do ,  Sanghoon Baek ,  Sang-Kyu Oh ,  Kwanyoung Chun ,  Sunyoung Park ,  Taejoong Song

IPC: H01L21/70 ,  H01L21/8238 ,  H01L27/092 ,  H01L27/02

CPC classification number: H01L21/823871 ,  H01L27/0207 ,  H01L27/092

Abstract: Provided is a method of fabricating a semiconductor device with a field effect transistor. The method may include forming a first gate electrode and a second gate electrode extending substantially parallel to each other and each crossing a PMOSFET region on a substrate and an NMOSFET region on the substrate; forming an interlayered insulating layer covering the first gate electrode and the second gate electrode; patterning the interlayered insulating layer to form a first sub contact hole on the first gate electrode, the first sub contact hole being positioned between the PMOSFET region and the NMOSFET region, when viewed in a plan view; and patterning the interlayered insulating layer to form a first gate contact hole and to expose a top surface of the second gate electrode, wherein the first sub contact hole and the first gate contact hole form a single communication hole.

公开(公告)号：US09490263B2

公开(公告)日：2016-11-08

申请号：US14312702

申请日：2014-06-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sooyeon Jeon ,  Rwik Sengupta ,  Chulhong Park ,  Kwanyoung Chun ,  Yusun Lee ,  Hyun-Jong Lee

IPC: H01L27/118 ,  H01L27/02

CPC classification number: H01L27/11807 ,  H01L27/0207 ,  H01L2027/11861 ,  H01L2027/11881

Abstract: A semiconductor device includes a substrate on which a plurality of logic cells are provided, and a plurality of active portions provided on the substrate and extending in a first direction. Contacts and gate structures extend in a second direction intersecting the first direction and are alternately arranged. A common conductive line extends along a boundary region of the plurality of logic cells in the first direction. At least one of the contacts is electrically connected to the common conductive line through a via therebetween, and each of the contacts intersects a plurality of the active portions. End portions of the contacts are aligned with each other along the first direction.

Abstract translation: 半导体器件包括其上设置有多个逻辑单元的基板和设置在基板上并沿第一方向延伸的多个有源部分。 触点和栅极结构在与第一方向相交的第二方向上延伸并且交替地布置。 公共导线沿第一方向沿多个逻辑单元的边界区域延伸。 至少一个触点通过它们之间的通孔电连接到公共导线，并且每个触点与多个有源部分相交。 触点的端部沿着第一方向彼此对准。

公开(公告)号：US12261166B2

公开(公告)日：2025-03-25

申请号：US18140115

申请日：2023-04-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jungkyu Chae ,  Kwanyoung Chun ,  Yoonjin Kim

IPC: H01L27/02

Abstract: A semiconductor device includes a pair of first and second dummy active regions extending in a first horizontal direction and spaced apart from each other in a second horizontal direction; a pair of first and second circuit active regions extending in the first horizontal direction and spaced apart in the second horizontal direction; and a plurality of line patterns extending in the second horizontal direction and spaced apart in the first horizontal direction. The pair of first and second dummy active regions may be between a pair of line patterns adjacent to each other among the plurality of line patterns. At least one of the first and second dummy active regions may have a width-changing portion in which a width of the at least one of the first and second dummy active regions changes in the second horizontal direction between the pair of line patterns adjacent to each other.

公开(公告)号：US11222158B2

公开(公告)日：2022-01-11

申请号：US17034634

申请日：2020-09-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jungkyu Chae ,  Jinwoo Jeong ,  Kwanyoung Chun

IPC: G06F30/392 ,  G06F30/3312 ,  H01L29/06 ,  G06F119/12 ,  H01L29/786 ,  G06F119/18 ,  H01L29/423

Abstract: A method of manufacturing an integrated circuit includes: generating layout data of the integrated circuit by placing and routing standard cells that define the integrated circuit, the standard cells including a nanosheet; generating timing analysis data by performing a timing analysis of the integrated circuit using the layout data; and regenerating the layout data of the integrated circuit by replacing and rerouting the standard cells that define the integrated circuit based on the timing analysis data and a shape of the nanosheet of the placed standard cells.

公开(公告)号：US20190288109A1

公开(公告)日：2019-09-19

申请号：US16364303

申请日：2019-03-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yeoncheol Heo ,  Sharma Deepak ,  Kwanyoung Chun

IPC: H01L29/78 ,  H01L29/423 ,  H01L29/10 ,  H01L21/8238 ,  H01L27/092 ,  H01L27/02 ,  H01L29/06

Abstract: A semiconductor device includes a substrate with an upper surface and a lower surface, and first to third active patterns extending from the upper surface of the substrate. The first to third active patterns are arranged adjacent to each other in a first direction. The second active pattern is disposed between the first and third active patterns. The semiconductor device also includes a first gate electrode surrounding side surfaces of the first and second active patterns, and a second gate electrode surrounding side surfaces of the third active pattern. Each of the first to third active patterns includes a first impurity region, a channel region, and a second impurity region.