公开(公告)号：US10236298B2

公开(公告)日：2019-03-19

申请号：US15997725

申请日：2018-06-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyun-Suk Kim ,  Joon-Hee Lee ,  Kee-Jeong Rho

IPC: H01L27/11573 ,  H01L49/02 ,  H01L27/11519 ,  H01L27/11526 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11582 ,  H01L27/11521 ,  H01L27/11568

Abstract: Provided is a vertical non-volatile memory device in which a capacitor constituting a peripheral circuit region is formed as a vertical type so that an area occupied by the capacitor in the entire device can be reduced as compared with a planar capacitor. Thus, a non-volatile memory device may be highly integrated and have a high capacity. The device includes a substrate having a cell region and a peripheral circuit region, a memory cell string including a plurality of vertical memory cells formed in the cell region and channel holes formed to penetrate the vertical memory cells in a first direction vertical to the substrate, an insulating layer formed in the peripheral circuit region on the substrates at substantially the same level as an upper surface of the memory cell string, and a plurality of capacitor electrodes formed on the peripheral circuit region to penetrate at least a portion of the insulating layer in the first direction, the plurality of capacitor electrodes extending parallel to the channel holes. The plurality of capacitor electrodes are spaced apart from one another in a second direction parallel to the substrate, and the insulating layer is interposed between a pair of adjacent capacitor electrodes from among the plurality of capacitor electrodes.

公开(公告)号：US10600805B2

公开(公告)日：2020-03-24

申请号：US16157684

申请日：2018-10-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Joo-Hee Park ,  Jong-Min Lee ,  Seon-Kyung Kim ,  Kee-Jeong Rho ,  Jin-hyun Shin ,  Jong-Hyun Park ,  Jin-Yeon Won

IPC: H01L27/11582 ,  H01L27/11565 ,  H01L27/1157

Abstract: A vertical memory device includes a substrate, a plurality of channels on the substrate and extending in a first direction that vertical to a top surface of the substrate, a plurality of gate lines and a conductive line on the substrate. The gate lines are stacked on top of each other. The gate lines surround the channels. The gate lines are spaced apart from each other along the first direction. The conductive line cuts the gate lines along the first direction. A width of the conductive line is periodically and repeatedly changed.

公开(公告)号：US11925015B2

公开(公告)日：2024-03-05

申请号：US17024987

申请日：2020-09-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sang-Yong Park ,  Kee-Jeong Rho ,  Hyeong Park ,  Tae-Wan Lim

IPC: H10B12/00 ,  H01L23/31 ,  H01L23/528 ,  H01L29/423 ,  H01L29/78 ,  H01L29/792 ,  H10B43/27 ,  H10B43/30 ,  H10B43/35 ,  H10B43/40 ,  H10B43/50

CPC classification number: H10B12/50 ,  H01L23/3171 ,  H01L23/3185 ,  H01L23/528 ,  H01L29/42352 ,  H01L29/4236 ,  H01L29/7827 ,  H01L29/7926 ,  H10B43/27 ,  H10B43/30 ,  H10B43/35 ,  H10B43/40 ,  H10B43/50 ,  H01L2924/0002 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Vertical memory devices, and methods of manufacturing the same, include providing a substrate including a cell array region and a peripheral circuit region, forming a mold structure in the cell array region, forming an opening for a common source line passing through the mold structure and extending in a first direction perpendicular to a top surface of the substrate, forming a first contact plug having an inner sidewall delimiting a recessed region in the opening for the common source line, and forming a common source bit line contact electrically connected to the inner sidewall of the first contact plug.