公开(公告)号：US20170005100A1

公开(公告)日：2017-01-05

申请号：US15139444

申请日：2016-04-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Min Hee CHO ,  Satoru YAMADA ,  Sung-Sam LEE ,  Jung-Bun LEE

IPC: H01L27/108

CPC classification number: H01L27/10897 ,  H01L23/522 ,  H01L23/5226

Abstract: A semiconductor device may include a plurality of dummy wirings formed on a substrate at different vertical levels and electrically floated and a plurality of dummy contact plugs each electrically connected between two adjacent dummy wirings of the plurality of dummy wiring of the plurality of dummy wirings. No dummy wiring of the plurality of dummy wirings is electrically connected to a terminal of any one of a plurality of transistors included in the substrate.

Abstract translation: 半导体器件可以包括形成在不同垂直级别的基板上的电浮置的多个虚拟布线和多个虚拟接触插塞，每个虚拟接触插头电连接在多个虚拟布线中的多个虚拟布线的两个相邻的虚拟布线之间。 多个虚拟布线的虚拟布线不与基板中包含的多个晶体管中的任一个晶体管的端子电连接。

公开(公告)号：US20160049398A1

公开(公告)日：2016-02-18

申请号：US14926223

申请日：2015-10-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sung-Ho JANG ,  Tae-Ho LEE ,  Jung-Bun LEE

IPC: H01L27/092 ,  H01L29/06

CPC classification number: H01L27/092 ,  H01L21/823842 ,  H01L21/823864 ,  H01L29/0649 ,  H01L29/4966 ,  H01L29/6656

Abstract: A semiconductor device including a substrate including an NMOS region and a PMOS region; first and second gate dielectrics on the NMOS and PMOS regions of the substrate and including a high-k dielectric material; a first gate structure on the first gate dielectric and including a sequentially stacked first n-type metal layer pattern and first electrode layer pattern; a second gate structure on the second gate dielectric and including a sequentially stacked p-type metal layer pattern, second n-type metal layer pattern, and second electrode layer pattern; first and second spacers on sidewalls of the first and second gate structures; a first offset pattern between the first gate structure and the first spacer; and a second offset pattern between the second gate structure and the second spacer, the second offset pattern being on the sidewalls of the second gate structure excluding sidewalls of the p-type metal layer pattern.

Abstract translation: 一种半导体器件，包括：包括NMOS区域和PMOS区域的衬底; 第一和第二栅极介质在衬底的NMOS和PMOS区域上并且包括高k电介质材料; 在所述第一栅极电介质上的第一栅极结构，并且包括顺序堆叠的第一n型金属层图案和第一电极层图案; 所述第二栅极结构在所述第二栅极电介质上并且包括顺序堆叠的p型金属层图案，第二n型金属层图案和第二电极层图案; 第一和第二栅极结构的侧壁上的第一和第二间隔物; 第一栅极结构和第一间隔物之间​​的第一偏移图案; 以及在所述第二栅极结构和所述第二间隔物之间​​的第二偏移图案，所述第二偏移图案位于除了所述p型金属层图案的侧壁之外的所述第二栅极结构的侧壁上。

公开(公告)号：US20140246729A1

公开(公告)日：2014-09-04

申请号：US14182876

申请日：2014-02-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sung-Ho JANG ,  Tae-Ho LEE ,  Jung-Bun LEE

IPC: H01L27/092

CPC classification number: H01L27/092 ,  H01L21/823842 ,  H01L21/823864 ,  H01L29/0649 ,  H01L29/4966 ,  H01L29/6656

Abstract: A semiconductor device including a substrate including an NMOS region and a PMOS region; first and second gate dielectrics on the NMOS and PMOS regions of the substrate and including a high-k dielectric material; a first gate structure on the first gate dielectric and including a sequentially stacked first n-type metal layer pattern and first electrode layer pattern; a second gate structure on the second gate dielectric and including a sequentially stacked p-type metal layer pattern, second n-type metal layer pattern, and second electrode layer pattern; first and second spacers on sidewalls of the first and second gate structures; a first offset pattern between the first gate structure and the first spacer; and a second offset pattern between the second gate structure and the second spacer, the second offset pattern being on the sidewalls of the second gate structure excluding sidewalls of the p-type metal layer pattern.

Abstract translation: 一种半导体器件，包括：包括NMOS区域和PMOS区域的衬底; 第一和第二栅极介质在衬底的NMOS和PMOS区域上并且包括高k电介质材料; 在所述第一栅极电介质上的第一栅极结构，并且包括顺序堆叠的第一n型金属层图案和第一电极层图案; 所述第二栅极结构在所述第二栅极电介质上并且包括顺序堆叠的p型金属层图案，第二n型金属层图案和第二电极层图案; 第一和第二栅极结构的侧壁上的第一和第二间隔物; 第一栅极结构和第一间隔物之间​​的第一偏移图案; 以及在所述第二栅极结构和所述第二间隔物之间​​的第二偏移图案，所述第二偏移图案位于除了所述p型金属层图案的侧壁之外的所述第二栅极结构的侧壁上。

公开(公告)号：US20140246724A1

公开(公告)日：2014-09-04

申请号：US14165775

申请日：2014-01-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sung-Ho JANG ,  Seung-Hun SON ,  Jung-Bun LEE

IPC: H01L27/108

CPC classification number: H01L27/10897 ,  G11C5/025 ,  G11C11/404 ,  G11C2211/4016 ,  H01L27/10894

Abstract: Memory devices include a substrate including first to third regions, a memory element on the first region, a first transistor on the second region closer to the first region than to the third region and including a spacer filled with an insulating material, and a second transistor on the third region and including a spacer filled with air.

Abstract translation: 存储器件包括包括第一至第三区域的衬底，第一区域上的存储元件，在第二区域上比第三区域更靠近第一区域的第一晶体管，并且包括填充有绝缘材料的间隔区，以及第二晶体管 并且包括填充有空气的间隔件。