公开(公告)号：US20170018451A1

公开(公告)日：2017-01-19

申请号：US15071228

申请日：2016-03-16

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Xinglong CHEN ,  Dali LIU ,  Sung-Ho JANG ,  Yong-Ho LIM

IPC: H01L21/687

CPC classification number: H01L21/68728

Abstract: A wafer clamping apparatus, including a plurality of support pins under a wafer, the plurality of pins to support the wafer; and a side clamp at a lateral side of the wafer, the side clamp to directly contact a lateral side of the wafer to press the wafer, the side clamp to press the wafer in a first direction or a second direction, the first direction and the second direction being different directions.

Abstract translation: 一种晶片夹持装置，包括晶片下面的多个支撑销，所述多个销支撑晶片; 以及在所述晶片的横向侧的侧夹具，所述侧夹具直接接触所述晶片的侧面以按压所述晶片，所述侧夹具将所述晶片沿第一方向或第二方向按第一方向和所述第二方向 第二个方向是不同的方向。

公开(公告)号：US20150123238A1

公开(公告)日：2015-05-07

申请号：US14465982

申请日：2014-08-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sung-Ho JANG ,  Dong-Jin LEE ,  Bong-Soo KIM ,  Jun-Hee LIM ,  Joon HAN

IPC: H01L23/485 ,  H01L23/48

CPC classification number: H01L27/108 ,  H01L27/10814 ,  H01L27/10823 ,  H01L27/10844 ,  H01L27/10855 ,  H01L27/10864 ,  H01L27/10876 ,  H01L27/10885 ,  H01L27/10888 ,  H01L27/10894 ,  H01L27/12 ,  H01L27/13 ,  H01L29/785

Abstract: There is provided a semiconductor device. The semiconductor device may include multiple contacts plugs, an insulation layer pattern, a metal oxide layer pattern, a metal pattern and a metal line. The contact plugs contact a substrate. The insulation layer pattern is formed between the contact plugs and has a top surface lower than those of the contact plugs. The metal oxide layer pattern is formed on the insulation layer pattern, and has a dielectric constant higher than that of silicon oxide. The metal pattern is formed on the metal oxide layer pattern and contacts sidewalls of the contact plugs. The metal line contacts top surfaces of the contact plugs and the metal pattern and extends thereon.

Abstract translation: 提供了一种半导体器件。 半导体器件可以包括多个触点插头，绝缘层图案，金属氧化物层图案，金属图案和金属线。 接触插头接触基板。 绝缘层图案形成在接触插塞之间，并且具有比接触插塞低的顶表面。 金属氧化物层图案形成在绝缘层图案上，并且具有比氧化硅更高的介电常数。 金属图案形成在金属氧化物层图案上并接触接触插塞的侧壁。 金属线接触接触插塞的顶表面和金属图案并在其上延伸。

公开(公告)号：US20160049398A1

公开(公告)日：2016-02-18

申请号：US14926223

申请日：2015-10-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sung-Ho JANG ,  Tae-Ho LEE ,  Jung-Bun LEE

IPC: H01L27/092 ,  H01L29/06

CPC classification number: H01L27/092 ,  H01L21/823842 ,  H01L21/823864 ,  H01L29/0649 ,  H01L29/4966 ,  H01L29/6656

Abstract: A semiconductor device including a substrate including an NMOS region and a PMOS region; first and second gate dielectrics on the NMOS and PMOS regions of the substrate and including a high-k dielectric material; a first gate structure on the first gate dielectric and including a sequentially stacked first n-type metal layer pattern and first electrode layer pattern; a second gate structure on the second gate dielectric and including a sequentially stacked p-type metal layer pattern, second n-type metal layer pattern, and second electrode layer pattern; first and second spacers on sidewalls of the first and second gate structures; a first offset pattern between the first gate structure and the first spacer; and a second offset pattern between the second gate structure and the second spacer, the second offset pattern being on the sidewalls of the second gate structure excluding sidewalls of the p-type metal layer pattern.

Abstract translation: 一种半导体器件，包括：包括NMOS区域和PMOS区域的衬底; 第一和第二栅极介质在衬底的NMOS和PMOS区域上并且包括高k电介质材料; 在所述第一栅极电介质上的第一栅极结构，并且包括顺序堆叠的第一n型金属层图案和第一电极层图案; 所述第二栅极结构在所述第二栅极电介质上并且包括顺序堆叠的p型金属层图案，第二n型金属层图案和第二电极层图案; 第一和第二栅极结构的侧壁上的第一和第二间隔物; 第一栅极结构和第一间隔物之间​​的第一偏移图案; 以及在所述第二栅极结构和所述第二间隔物之间​​的第二偏移图案，所述第二偏移图案位于除了所述p型金属层图案的侧壁之外的所述第二栅极结构的侧壁上。

公开(公告)号：US20140246729A1

公开(公告)日：2014-09-04

申请号：US14182876

申请日：2014-02-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sung-Ho JANG ,  Tae-Ho LEE ,  Jung-Bun LEE

IPC: H01L27/092

CPC classification number: H01L27/092 ,  H01L21/823842 ,  H01L21/823864 ,  H01L29/0649 ,  H01L29/4966 ,  H01L29/6656

Abstract: A semiconductor device including a substrate including an NMOS region and a PMOS region; first and second gate dielectrics on the NMOS and PMOS regions of the substrate and including a high-k dielectric material; a first gate structure on the first gate dielectric and including a sequentially stacked first n-type metal layer pattern and first electrode layer pattern; a second gate structure on the second gate dielectric and including a sequentially stacked p-type metal layer pattern, second n-type metal layer pattern, and second electrode layer pattern; first and second spacers on sidewalls of the first and second gate structures; a first offset pattern between the first gate structure and the first spacer; and a second offset pattern between the second gate structure and the second spacer, the second offset pattern being on the sidewalls of the second gate structure excluding sidewalls of the p-type metal layer pattern.

Abstract translation: 一种半导体器件，包括：包括NMOS区域和PMOS区域的衬底; 第一和第二栅极介质在衬底的NMOS和PMOS区域上并且包括高k电介质材料; 在所述第一栅极电介质上的第一栅极结构，并且包括顺序堆叠的第一n型金属层图案和第一电极层图案; 所述第二栅极结构在所述第二栅极电介质上并且包括顺序堆叠的p型金属层图案，第二n型金属层图案和第二电极层图案; 第一和第二栅极结构的侧壁上的第一和第二间隔物; 第一栅极结构和第一间隔物之间​​的第一偏移图案; 以及在所述第二栅极结构和所述第二间隔物之间​​的第二偏移图案，所述第二偏移图案位于除了所述p型金属层图案的侧壁之外的所述第二栅极结构的侧壁上。

公开(公告)号：US20140246724A1

公开(公告)日：2014-09-04

申请号：US14165775

申请日：2014-01-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sung-Ho JANG ,  Seung-Hun SON ,  Jung-Bun LEE

IPC: H01L27/108

CPC classification number: H01L27/10897 ,  G11C5/025 ,  G11C11/404 ,  G11C2211/4016 ,  H01L27/10894

Abstract: Memory devices include a substrate including first to third regions, a memory element on the first region, a first transistor on the second region closer to the first region than to the third region and including a spacer filled with an insulating material, and a second transistor on the third region and including a spacer filled with air.

Abstract translation: 存储器件包括包括第一至第三区域的衬底，第一区域上的存储元件，在第二区域上比第三区域更靠近第一区域的第一晶体管，并且包括填充有绝缘材料的间隔区，以及第二晶体管 并且包括填充有空气的间隔件。