公开(公告)号：US10971395B2

公开(公告)日：2021-04-06

申请号：US16271120

申请日：2019-02-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Moon Keun Kim ,  Jae Wha Park ,  Jun Kwan Kim ,  Hyo Jeong Moon ,  Seung Jong Park ,  Seul Gi Bae

IPC: H01L21/768 ,  H01L23/532 ,  H01L21/02 ,  H01L23/522

Abstract: A method for fabricating a semiconductor device includes forming a first wiring layer, the first wiring layer including a first metal wiring and a first interlayer insulating film wrapping the first metal wiring on a substrate, forming a first via layer, the first via layer including a first via that is in electrical connection with the first metal wiring, and a second interlayer insulating film wrapping the first via on the first wiring layer, and forming a second wiring layer, the second wiring layer including a second metal wiring that is in electrical connection with the first via, and a third interlayer insulating film wrapping the second metal wiring on the first via layer, wherein the third interlayer insulating film contains deuterium and is formed through chemical vapor deposition using a first gas containing deuterium and a second gas containing hydrogen.

公开(公告)号：US12211795B2

公开(公告)日：2025-01-28

申请号：US17509636

申请日：2021-10-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jinsub Kim ,  Kyoung-Hee Kim ,  Munjun Kim ,  Jun Kwan Kim ,  Woo Choel Noh

IPC: H01L23/532 ,  H01L21/768 ,  H01L23/522 ,  H10B12/00

Abstract: A semiconductor device includes a substrate including a cell array region and a peripheral circuit region, capacitors on the cell array region of the substrate, peripheral transistors on the peripheral circuit region of the substrate, a first upper interlayer insulating layer on the capacitors and the peripheral transistors, a first upper contact electrically connected to at least one of the peripheral transistors, the first upper contact penetrating the first upper interlayer insulating layer, a first upper interconnection line provided on the first upper interlayer insulating layer and electrically connected to the first upper contact, a second upper interlayer insulating layer covering the first upper interconnection line, and a first blocking layer between the first upper interlayer insulating layer and the second upper interlayer insulating layer. The first blocking layer is absent between the first upper interconnection line and the first upper interlayer insulating layer.

公开(公告)号：US12016178B2

公开(公告)日：2024-06-18

申请号：US18097592

申请日：2023-01-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kyoung-Hee Kim ,  Woo Choel Noh ,  Ik Soo Kim ,  Jun Kwan Kim ,  Jinsub Kim ,  Yongjin Shin

IPC: H10B41/46 ,  H10B41/10 ,  H10B41/20 ,  H10B43/10 ,  H10B43/20 ,  H10B43/40

CPC classification number: H10B41/46 ,  H10B41/10 ,  H10B41/20 ,  H10B43/10 ,  H10B43/20 ,  H10B43/40

Abstract: A semiconductor device including a substrate that includes a cell array region and a peripheral circuit region; a cell transistor on the cell array region of the substrate; a peripheral transistor on the peripheral circuit region of the substrate; a first interconnection layer connected to the cell transistor; a second interconnection layer connected to the peripheral transistor; an interlayer dielectric layer covering the first interconnection layer; and a blocking layer spaced apart from the first interconnection layer, the blocking layer covering a top surface and a sidewall of the second interconnection layer.

公开(公告)号：US11700726B2

公开(公告)日：2023-07-11

申请号：US17165539

申请日：2021-02-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jin Sub Kim ,  Jun Kwan Kim ,  Woo Choel Noh ,  Kyoung-Hee Kim ,  Ik Soo Kim ,  Yong Jin Shin

IPC: H10B12/00 ,  H01L27/108

CPC classification number: H01L27/10814 ,  H01L27/10823 ,  H01L27/10852 ,  H01L27/10897

Abstract: A semiconductor device includes a lower electrode on a substrate, a capacitor dielectric film extending on the lower electrode along a side surface of the lower electrode that is perpendicular to the substrate, an upper electrode on the capacitor dielectric film, an interface layer including a hydrogen blocking film and a hydrogen bypass film on the upper electrode, the hydrogen blocking film including a conductive material, and a contact plug penetrating the interface layer and electrically connected to the upper electrode.

公开(公告)号：US11563017B2

公开(公告)日：2023-01-24

申请号：US17099994

申请日：2020-11-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kyoung-Hee Kim ,  Woo Choel Noh ,  Ik Soo Kim ,  Jun Kwan Kim ,  Jinsub Kim ,  Yongjin Shin

IPC: H01L27/11539 ,  H01L27/11519 ,  H01L27/11578 ,  H01L27/11565 ,  H01L27/11573 ,  H01L27/11551

Abstract: A semiconductor device including a substrate that includes a cell array region and a peripheral circuit region; a cell transistor on the cell array region of the substrate; a peripheral transistor on the peripheral circuit region of the substrate; a first interconnection layer connected to the cell transistor; a second interconnection layer connected to the peripheral transistor; an interlayer dielectric layer covering the first interconnection layer; and a blocking layer spaced apart from the first interconnection layer, the blocking layer covering a top surface and a sidewall of the second interconnection layer.

公开(公告)号：US11557513B2

公开(公告)日：2023-01-17

申请号：US17215365

申请日：2021-03-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Moon Keun Kim ,  Jae Wha Park ,  Jun Kwan Kim ,  Hyo Jeong Moon ,  Seung Jong Park ,  Seul Gi Bae

IPC: H01L21/768 ,  H01L23/532 ,  H01L21/02 ,  H01L23/522

Abstract: A method for fabricating a semiconductor device includes forming a first wiring layer, the first wiring layer including a first metal wiring and a first interlayer insulating film wrapping the first metal wiring on a substrate, forming a first via layer, the first via layer including a first via that is in electrical connection with the first metal wiring, and a second interlayer insulating film wrapping the first via on the first wiring layer, and forming a second wiring layer, the second wiring layer including a second metal wiring that is in electrical connection with the first via, and a third interlayer insulating film wrapping the second metal wiring on the first via layer, wherein the third interlayer insulating film contains deuterium and is formed through chemical vapor deposition using a first gas containing deuterium and a second gas containing hydrogen.

公开(公告)号：US10566284B2

公开(公告)日：2020-02-18

申请号：US16027484

申请日：2018-07-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jun Kwan Kim ,  Sanghoon Ahn ,  Kyu-Hee Han ,  JaeWha Park ,  Heesook Park

IPC: H01L23/532 ,  H01L23/522

Abstract: Provided is a semiconductor device comprising a device region on a substrate, an interlayer dielectric layer on the device region, a first interface layer on a side of the interlayer dielectric layer, a low-k dielectric layer spaced apart from the interlayer dielectric layer across the first interface layer and having a dielectric constant less than that of the interlayer dielectric layer, and a conductive line in the low-k dielectric layer. The first interface layer comprises a first sub-interface layer in contact with the low-k dielectric layer, and a second sub-interface layer in contact with the interlayer dielectric layer. The second sub-interface layer has hydrogen permeability less than that of the first sub-interface layer.