公开(公告)号：US20250159897A1

公开(公告)日：2025-05-15

申请号：US18667010

申请日：2024-05-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Youngji NOH ,  Jongho WOO

IPC: H10B51/30 ,  H01L23/00 ,  H01L25/00 ,  H01L25/065 ,  H01L25/18 ,  H10B51/20 ,  H10B80/00

Abstract: A semiconductor device includes a stack structure including interlayer insulating layers and gate electrodes stacked in a vertical direction; a plate layer on the stack structure; vertical structures respectively including a back gate electrode penetrating the stack structure and the plate layer in the vertical direction, a channel layer between the back gate electrode and the gate electrodes, and a gate dielectric structure including a ferroelectric layer between the channel layer and gate electrodes; a first horizontal insulating layer on upper surfaces of the plate layer and channel layer; a second horizontal insulating layer on the first horizontal insulating layer and including a material different than the first horizontal insulating layer; and back gate contacts on the respective vertical structures, connected to respective ones of the back gate electrodes, and including a pad region in the second horizontal insulating layer and a via region protruding upwardly from the pad region.

公开(公告)号：US20240164116A1

公开(公告)日：2024-05-16

申请号：US18215280

申请日：2023-06-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Youngji NOH ,  Jongho WOO ,  Joo-Heon KANG ,  Kyunghoon KIM ,  Myunghun WOO

IPC: H10B63/00

CPC classification number: H10B63/845 ,  H10B63/34

Abstract: A semiconductor device includes a gate stacked structure including gate patterns and insulating patterns that are alternately stacked with each other; a gate insulating layer on a sidewall of the gate stacked structure; a channel layer surrounded by the gate insulating layer; a source line surrounded by the channel layer; a variable resistive layer surrounded by the channel layer; and a drain line surrounded by the channel layer.

公开(公告)号：US20240032303A1

公开(公告)日：2024-01-25

申请号：US18301597

申请日：2023-04-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jongho WOO ,  Youngji Noh ,  Minjun Lee

IPC: H10B51/20 ,  H10B51/30 ,  H10B51/40

CPC classification number: H10B51/20 ,  H10B51/30 ,  H10B51/40

Abstract: A three-dimensional semiconductor device includes a plate common source line, first and second word lines spaced apart from each other to at least partially define a vertical space therebetween, a channel pattern in the vertical space, a ferroelectric layer including a first portion between the channel pattern and the first word line, a second portion between the channel pattern and the second word line, and a third portion contacting the plate common source line, a bit line in the vertical space to contact the channel pattern and having a first width in a first horizontal direction, and a source line spaced apart from the bit line in the vertical space to contact the channel pattern, having a second width greater than the first width in the first horizontal direction, and having a source line contact portion inside the plate common source line.

公开(公告)号：US20240260280A1

公开(公告)日：2024-08-01

申请号：US18457799

申请日：2023-08-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Youngji NOH ,  Jongho WOO ,  Joo-Heon KANG ,  Myunghun WOO

IPC: H10B63/00

CPC classification number: H10B63/845 ,  H10B63/34

Abstract: A semiconductor device including a cell array structure on a semiconductor substrate, the cell array structure including an electrode structure including electrodes and insulating layers vertically and alternately stacked on the semiconductor substrate, and a vertical structure and a penetration contact plug penetrating the electrode structure may be provided. The vertical structure may include a first inner layer, a first outer layer, and a first intermediate layer, and the penetration contact plug may include a second inner layer, a second outer layer, and a second intermediate layer. The electrodes may include a doped semiconductor material, and the first and second outer layers may include the same material. The first and second intermediate layers may include the same material, and the first and second inner layers may include materials different from each other.

公开(公告)号：US20230269942A1

公开(公告)日：2023-08-24

申请号：US18096257

申请日：2023-01-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Myunghun WOO ,  Jooheon KANG ,  Hyunmog PARK ,  Jongho WOO ,  Suseong NOH ,  Youngji NOH

IPC: H10B43/27 ,  H10B43/40 ,  H10B43/35 ,  H10B41/27 ,  H10B41/49 ,  H10B41/35

CPC classification number: H10B43/27 ,  H10B43/40 ,  H10B43/35 ,  H10B41/27 ,  H10B41/49 ,  H10B41/35

Abstract: A semiconductor device includes a gate stack structure including alternately stacked insulating patterns and conductive patterns; a memory channel structure extending through the gate stack structure; and a bit line pad on the memory channel structure, wherein the memory channel structure includes a variable resistance layer, a channel layer surrounding the variable resistance layer, and a channel insulating layer surrounding the channel layer, and a bottom surface of the bit line pad contacts a top surface of the variable resistance layer, a top surface of the channel layer, and a top surface of the channel insulating layer.

公开(公告)号：US20250071991A1

公开(公告)日：2025-02-27

申请号：US18583121

申请日：2024-02-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sangwoo HAN ,  Jongho WOO ,  Seung Min LEE ,  Moonkang CHOI

IPC: H10B43/27 ,  H01L25/065 ,  H10B43/10 ,  H10B43/35 ,  H10B51/10 ,  H10B51/20 ,  H10B80/00

Abstract: A semiconductor device includes a source structure comprising a first source layer, a second source layer on the first source layer, and a third source layer on the second source layer, a gate stack structure on the source structure, the gate stack structure with alternating insulating patterns and conductive patterns, and a memory channel structure penetrating the gate stack structure. The memory channel structure includes a channel layer and a memory layer surrounding the channel layer. The channel layer penetrates the memory layer and the second source layer, and a bottom surface of the channel layer is in contact with the source structure.

公开(公告)号：US20250063731A1

公开(公告)日：2025-02-20

申请号：US18650189

申请日：2024-04-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sangwoo HAN ,  Jongho WOO ,  Seung Min LEE ,  Moonkang CHOI

IPC: H10B43/27 ,  H01L25/065 ,  H10B43/10 ,  H10B43/35 ,  H10B51/10 ,  H10B51/20 ,  H10B80/00

Abstract: A semiconductor device includes a source structure having a first source layer, a second source layer on the first source layer, and a third source layer on the second source layer. A gate stack structure is on the source structure. The gate stack structure includes dielectric patterns and conductive patterns that are alternately stacked. A memory channel structure penetrates the gate stack structure. The memory channel structure includes a channel layer. A data storage layer surrounds the channel layer. A blocking layer surrounds the data storage layer. The second source layer includes an inner sidewall directly contacting the channel layer. The third source layer includes an inner sidewall directly contacting the data storage layer.