公开(公告)号：US20240203813A1

公开(公告)日：2024-06-20

申请号：US18364434

申请日：2023-08-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Wooseup HWANG ,  Jihye SHIM

IPC: H01L23/31 ,  H01L23/00 ,  H01L23/48 ,  H01L25/065

CPC classification number: H01L23/3171 ,  H01L23/481 ,  H01L24/30 ,  H01L24/32 ,  H01L25/0657 ,  H01L24/14 ,  H01L24/16 ,  H01L24/73 ,  H01L2224/14181 ,  H01L2224/16145 ,  H01L2224/30181 ,  H01L2224/32145 ,  H01L2224/73204

Abstract: A semiconductor package includes a first semiconductor die, second semiconductor dies each of which has a width less than a width of the first semiconductor die and which are stacked on the first semiconductor die, a first non-conductive layer between the first semiconductor die and a lowermost second semiconductor die, and a second non-conductive layer between adjacent ones of the second semiconductor dies. Each of the second semiconductor dies includes a first substrate that has a first front surface and a first rear surface, a first interlayer dielectric layer that covers the first front surface, first through electrodes that penetrate the first substrate, and a first passivation layer that covers the first rear surface. A first groove is in the first passivation layer and a portion of the first substrate. The second non-conductive layer is within the first groove.

公开(公告)号：US20250105133A1

公开(公告)日：2025-03-27

申请号：US18828196

申请日：2024-09-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jinyoung KIM ,  Okseon YOON ,  Jiyoung YOON ,  Kiseok KIM ,  Jihye SHIM

IPC: H01L23/498 ,  H01L23/00 ,  H01L23/31 ,  H01L25/03

Abstract: A semiconductor package includes a redistribution structure including a redistribution layer including copper (Cu) and an insulating layer surrounding the redistribution layer, a semiconductor chip mounted on the redistribution structure and including connection pads, internal connection terminals between the redistribution structure and the semiconductor chip electrically connecting the redistribution layer to the connection pads, external connection terminals attached under the redistribution structure and electrically connected to the redistribution layer, and an encapsulant configured to surround the semiconductor chip and the internal connection terminals on the redistribution structure. The insulating layer includes an insulating material of which K is 20 to 100 in a TC index according to equation below. K = U T ( α 1 - α 2 ) × Δ ⁢ T × E [ TC ⁢ INDEX ]

公开(公告)号：US20240038549A1

公开(公告)日：2024-02-01

申请号：US18125958

申请日：2023-03-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jakyoung GU ,  Minsoo KIM ,  Jihye SHIM ,  Kyoungok JUNG

IPC: H01L21/48 ,  H01L25/10 ,  H10B80/00

CPC classification number: H01L21/4857 ,  H01L25/105 ,  H10B80/00 ,  H01L2225/1035 ,  H01L24/16

Abstract: A method of manufacturing a semiconductor package includes forming a plurality of conductive patterns on a substrate, forming a photoresist film over the substrate to cover the plurality of conductive patterns, forming a photoresist pattern from the photoresist film by a photolithography process using a photomask that includes a transparent area, a light-shielding area, and a semi-transparent area transmitting only a portion of light incident thereon, wherein the photoresist pattern includes a via hole, which exposes one conductive pattern, and a recessed portion, which has a lower surface exposing a portion of the photoresist pattern, forming a conductive post in the via hole, and removing the photoresist pattern by using a photoresist stripping composition.

公开(公告)号：US20250118639A1

公开(公告)日：2025-04-10

申请号：US18672349

申请日：2024-05-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyunjo KIM ,  Junhyeong PARK ,  Sunhyung KIM ,  Jieun PARK ,  Jihye SHIM ,  Yuseon HEO

IPC: H01L23/498 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31

Abstract: A semiconductor package includes a first redistribution structure including upper pads; a semiconductor chip disposed on the first redistribution structure; an encapsulant on the first redistribution structure and surrounding the semiconductor chip; a second redistribution structure disposed on the encapsulant and including an upper redistribution layer; a plurality of posts penetrating the encapsulant and electrically connecting the upper pads of the first redistribution structure to the upper redistribution layer of the second redistribution structure; metal layers between the upper pads and the plurality of posts and having an upper surface having a first step difference with an upper surface of an edge of the upper pads; and a seed layer between the metal layers and the plurality of posts.

公开(公告)号：US20240194553A1

公开(公告)日：2024-06-13

申请号：US18374123

申请日：2023-09-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jinyoung KIM ,  Wonbin SHIN ,  Kiseok KIM ,  Jihye SHIM

IPC: H01L23/31 ,  H01L23/00 ,  H01L23/29 ,  H01L23/498 ,  H01L25/065 ,  H01L25/10 ,  H01L25/16 ,  H10B80/00

CPC classification number: H01L23/3135 ,  H01L23/296 ,  H01L23/49816 ,  H01L23/49822 ,  H01L24/08 ,  H01L24/29 ,  H01L24/32 ,  H01L24/80 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/162 ,  H10B80/00 ,  H01L24/16 ,  H01L2224/08113 ,  H01L2224/08145 ,  H01L2224/08225 ,  H01L2224/16227 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2224/97 ,  H01L2225/06541 ,  H01L2225/06548 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/1431 ,  H01L2924/1436 ,  H01L2924/1437 ,  H01L2924/1438 ,  H01L2924/3511

Abstract: A semiconductor package includes a first chip including a first substrate, a first wiring layer on the first substrate, and a plurality of through-electrodes to be connected to the first wiring layer and protruding from a lower surface of the first substrate, a double gap-fill layer covering a side surface and a lower surface of the first chip and a protruding portion of the through-electrode and having a double layer structure, a second chip disposed on the first chip and the double gap-fill layer, including a second wiring layer and a second substrate on the second wiring layer, and bonded to the first chip by hybrid bonding, and a bump on a lower surface of the first chip and connected to the through-electrode.

公开(公告)号：US20230126003A1

公开(公告)日：2023-04-27

申请号：US17858536

申请日：2022-07-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Junghoon KANG ,  Jihye SHIM ,  Jung Hyun LEE ,  Hyunchul JUNG

IPC: H01L23/544 ,  H01L25/10 ,  H01L23/498 ,  H01L21/56 ,  H01L23/31

Abstract: A semiconductor package including a lower substrate, a lower semiconductor chip mounted on the lower substrate, a lower mold layer on the lower substrate and enclosing the lower semiconductor chip, a redistribution layer on the lower mold layer, and a vertical connection terminal around the lower semiconductor chip and connecting the lower substrate to the redistribution layer may be provided. The lower semiconductor chip may include a cognition mark at a top surface thereof. The cognition mark may include a marking pattern having an intaglio shape at the top surface of the lower semiconductor chip, and a molding pattern filling an inner space of the marking pattern. A first material constituting the molding pattern may be the same as a second material constituting the lower mold layer.