公开(公告)号：US20230083493A1

公开(公告)日：2023-03-16

申请号：US17741581

申请日：2022-05-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seungwan SHIN ,  Junghoon KANG ,  Gun LEE

IPC: H01L23/00 ,  H01L25/065 ,  H01L23/31 ,  H01L23/29 ,  H01L23/532

Abstract: A semiconductor package includes: a lower redistribution structure including a lower insulating layer and a lower redistribution layer; a semiconductor chip disposed on the lower redistribution structure; connection conductors connected to the lower redistribution layer; an encapsulant disposed on the connection conductors; and an upper redistribution structure including an upper insulating layer and upper redistribution layers, wherein the upper insulating layer is disposed on the encapsulant, wherein the upper redistribution layers are disposed on the upper insulating layer, wherein the connection conductors and the encapsulant form a first step, wherein the upper redistribution layers include first and second upper redistribution layers, wherein the first upper redistribution layer does not overlap the connection conductors, wherein the second upper redistribution layer overlaps the connection conductors, wherein the first and second upper redistribution layers form a second step with a height substantially equal to or smaller than that of the first step.

公开(公告)号：US20230082004A1

公开(公告)日：2023-03-16

申请号：US17874527

申请日：2022-07-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Junghyun LEE ,  Junghoon KANG ,  Hyunchul JUNG

IPC: H01L21/56 ,  H01L23/498

Abstract: A method for manufacturing a semiconductor package includes forming a pad pattern including a metal film on a semiconductor chip; forming an insulating layer covering the pad pattern and including an organic insulating material; and forming an opening exposing a surface of the metal film of the pad pattern by performing laser processing on the insulating layer, wherein, in forming the opening, a region to be plastically deformed on the metal film by the laser processing is formed.

公开(公告)号：US20250157902A1

公开(公告)日：2025-05-15

申请号：US18938811

申请日：2024-11-06

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Junghoon KANG ,  Kiju LEE

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/31 ,  H01L23/538

Abstract: A semiconductor package includes: a first redistribution structure; a second redistribution structure arranged on the first redistribution structure; a first conductive pillar arranged spaced apart from the second redistribution structure and arranged on the first redistribution structure; a first chip arranged on the second redistribution structure; a first molding member covering the first chip and disposed on the second redistribution structure; a third redistribution structure arranged on the first molding member; a second chip arranged on the third redistribution structure; a second molding member covering the first conductive pillar and the first molding member; and a fourth redistribution structure arranged on the second molding member, wherein a first film is arranged on a first surface of the first conductive pillar, and the first film includes tin (Sn).

公开(公告)号：US20250015062A1

公开(公告)日：2025-01-09

申请号：US18421723

申请日：2024-01-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Junghoon KANG

IPC: H01L25/10 ,  H01L23/00 ,  H01L23/15 ,  H01L23/31 ,  H01L23/48 ,  H01L23/498 ,  H01L23/538 ,  H01L25/065

Abstract: A semiconductor package includes: a first redistribution substrate; a module structure on the first redistribution substrate; a first molding layer on the first redistribution substrate and surrounding the module structure; and a vertical connection structure on a side of the module structure, the vertical connection structure vertically extending and connected to the first redistribution substrate, wherein the module structure includes: an interposer substrate including a glass substrate, and a first semiconductor chip mounted on the interposer substrate; and a second semiconductor chip mounted on the interposer substrate.

公开(公告)号：US20230146085A1

公开(公告)日：2023-05-11

申请号：US17840744

申请日：2022-06-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Junghoon KANG ,  Byungmin YU ,  Junghyun LEE

IPC: H01L25/10 ,  H01L23/31 ,  H01L23/498 ,  H01L23/00 ,  H01L23/538

CPC classification number: H01L25/105 ,  H01L23/3128 ,  H01L23/49811 ,  H01L23/49822 ,  H01L23/49838 ,  H01L24/16 ,  H01L23/5385 ,  H01L2224/16227 ,  H01L2224/0401 ,  H01L2224/05599 ,  H01L2224/13099 ,  H01L2224/81399 ,  H01L24/05 ,  H01L24/13 ,  H01L24/81

Abstract: A semiconductor package includes: a lower redistribution structure including a lower redistribution insulation layer, a bump pad in the lower redistribution insulation layer, and a lower redistribution pattern electrically connected to the bump pad, wherein the lower redistribution insulation layer includes: one or more sidewalls at least partially defining a cavity extending from a bottom surface of the lower redistribution insulation layer to an upper surface of the lower redistribution insulation layer; a passive component in the cavity of the lower redistribution insulation layer; an insulation filler in the cavity of the lower redistribution insulation layer, the insulation filler covering sidewalls of the passive component; a first semiconductor chip on the lower redistribution structure, the first semiconductor chip electrically connected to both the lower redistribution pattern and the passive component; and an external connection bump connected to the bump pad via a pad opening of the lower redistribution insulation layer.

公开(公告)号：US20240429066A1

公开(公告)日：2024-12-26

申请号：US18415116

申请日：2024-01-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Junghoon KANG

IPC: H01L21/48 ,  H01L23/00 ,  H01L23/36

Abstract: A method of fabricating a semiconductor package is disclosed. The method may include providing an insulating layer, forming a seed layer to cover a top surface of the insulating layer, forming a sacrificial layer on the seed layer, forming penetration holes to penetrate the sacrificial layer and expose the seed layer, forming conductive posts in the penetration holes, removing the sacrificial layer, performing a laser irradiation process on the seed layer to form seed patterns below the conductive posts, attaching a semiconductor chip to a portion of the insulating layer which is placed between the conductive posts, and removing the insulating layer. An outer side surface of the conductive post and an outer side surface of the seed pattern may be substantially coplanar with each other, thereby forming a flat surface.

公开(公告)号：US20240421099A1

公开(公告)日：2024-12-19

申请号：US18816215

申请日：2024-08-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Junghoon KANG

IPC: H01L23/544 ,  H01L23/00 ,  H01L23/31 ,  H01L23/538 ,  H01L25/065

Abstract: A semiconductor package includes a first semiconductor chip; an encapsulant covering at least a portion of the first semiconductor chip; insulating layers provided on the encapsulant, each of the insulating layers being transparent or translucent; and wiring layers provided on the encapsulant, the wiring layers being partially covered by the insulating layers, wherein an outermost insulating layer of the insulating layers comprises a first region and a second region, a color of the first region is different from a color of the second region, the second region surrounds the first region, and at least one marking pattern comprising at least one step portion is provided in the first region of the outermost insulating layer.

公开(公告)号：US20230126003A1

公开(公告)日：2023-04-27

申请号：US17858536

申请日：2022-07-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Junghoon KANG ,  Jihye SHIM ,  Jung Hyun LEE ,  Hyunchul JUNG

IPC: H01L23/544 ,  H01L25/10 ,  H01L23/498 ,  H01L21/56 ,  H01L23/31

Abstract: A semiconductor package including a lower substrate, a lower semiconductor chip mounted on the lower substrate, a lower mold layer on the lower substrate and enclosing the lower semiconductor chip, a redistribution layer on the lower mold layer, and a vertical connection terminal around the lower semiconductor chip and connecting the lower substrate to the redistribution layer may be provided. The lower semiconductor chip may include a cognition mark at a top surface thereof. The cognition mark may include a marking pattern having an intaglio shape at the top surface of the lower semiconductor chip, and a molding pattern filling an inner space of the marking pattern. A first material constituting the molding pattern may be the same as a second material constituting the lower mold layer.

公开(公告)号：US20250167128A1

公开(公告)日：2025-05-22

申请号：US18808327

申请日：2024-08-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Junghoon KANG ,  Kiju LEE

IPC: H01L23/544 ,  H01L23/31 ,  H01L23/498

Abstract: A semiconductor package includes a package body, a semiconductor chip disposed in the package body, a first redistribution structure disposed on a lower surface of the package body and on a lower surface of the semiconductor chip, wherein the first redistribution structure includes a first redistribution element, a first redistribution pad disposed on a lower surface of the first redistribution structure and electrically connected to the first redistribution element, a ball land layer disposed on a lower surface of the first redistribution pad, a first pad insulating layer disposed on the lower surface of the first redistribution structure, wherein the first pad insulating layer insulates the first redistribution pad and the ball land layer, an alignment mark structure spaced apart from the first redistribution pad and the ball land layer and disposed inside or on a lower surface of the first pad insulating layer, and a first solder ball disposed on a lower surface of each of the first redistribution pad and the ball land layer.

公开(公告)号：US20250105231A1

公开(公告)日：2025-03-27

申请号：US18772409

申请日：2024-07-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Junghoon KANG ,  Daegon KIM

IPC: H01L25/16 ,  H01L23/00 ,  H01L23/31 ,  H01L23/48 ,  H01L23/498

Abstract: A semiconductor package including a package substrate defining a groove extending from an upper surface of the package substrate into the package substrate; a photonic integrated circuit (PIC) chip inside the groove of the package substrate; an interposer above the PIC chip and the package substrate, the interposer including a core substrate; an electronic integrated circuit (EIC) chip inside the interposer; and a semiconductor chip above the interposer. The interposer defines a cavity extending from an upper surface of the core substrate to a lower surface of the core substrate, and the EIC chip is inside the cavity of the core substrate.