公开(公告)号：US20130099255A1

公开(公告)日：2013-04-25

申请号：US13660947

申请日：2012-10-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jong Hyun LEE ,  Jung Hyun LEE ,  Ki Sung KIM ,  Suk Ho YOON ,  Young Sun KIM

IPC: H01L33/00

CPC classification number: C23C16/407 ,  C23C16/45578 ,  H01L33/32 ,  H01L33/42 ,  H01L2933/0016

Abstract: There is provided a semiconductor light emitting device having a zinc oxide-based transparent conductive thin film in which a Group III element is doped to have waveforms having a plurality of periods in a thickness direction.

Abstract translation: 提供了一种具有氧化锌基透明导电薄膜的半导体发光器件，其中掺杂了III族元素以具有在厚度方向上具有多个周期的波形。

公开(公告)号：US20240273218A1

公开(公告)日：2024-08-15

申请号：US18498667

申请日：2023-10-31

Applicant: Samsung Electronics Co., Ltd. ,  Seoul National University R&DB Foundation ,  Daegu Gyeongbuk Institute of Science and Technology ,  Industry Academic Cooperation Foundation, Chosun University

Inventor： Jong Seon NO ,  Eun Sang LEE ,  Joon Woo LEE ,  Young Sik KIM ,  Yongjune KIM ,  Jung Hyun LEE

IPC: G06F21/60 ,  G06F7/487 ,  G06F17/15

CPC classification number: G06F21/602 ,  G06F7/4876 ,  G06F17/156

Abstract: An apparatus with a neural network operation of homomorphic encrypted data includes: one or more processors configured to: generate homomorphic conjugation data of encrypted data based on the encrypted data, wherein the encrypted data corresponds to an output of each of a plurality of layers included in a neural network; and remove noise of the encrypted data based on the encrypted data and the homomorphic conjugation data.

公开(公告)号：US20240211737A1

公开(公告)日：2024-06-27

申请号：US18470589

申请日：2023-09-20

Applicant: SAMSUNG ELECTRONICS CO., LTD. ,  Seoul National University R&DB Foundation ,  Daegu Gyeongbuk Institute of Science and Technology ,  Industry Academic Cooperation Foundation, Chosun University

Inventor： Jong Seon NO ,  Yongjune KIM ,  Eun Sang LEE ,  Jung Hyun LEE ,  Young Sik KIM ,  Joon Woo LEE

IPC: G06N3/048 ,  G06F17/17 ,  H04L9/00

CPC classification number: G06N3/048 ,  G06F17/17 ,  H04L9/008

Abstract: An apparatus includes one or more processors configured to execute instructions; and one or more memories storing the instructions; wherein the execution of the instructions by the one or more processors configures the one or more processors to generate an approximate polynomial, approximating a neural network operation, of a portion of a deep neural network model that is configured to receive input data, by using weighted least squares based on parameters corresponding to the generation of the approximate polynomial, a mean of the input data, and a standard deviation of the input data; and generate a homomorphic encrypted data operation result based on the input data and the approximate polynomial that approximates the neural network operation.

公开(公告)号：US20230126003A1

公开(公告)日：2023-04-27

申请号：US17858536

申请日：2022-07-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Junghoon KANG ,  Jihye SHIM ,  Jung Hyun LEE ,  Hyunchul JUNG

IPC: H01L23/544 ,  H01L25/10 ,  H01L23/498 ,  H01L21/56 ,  H01L23/31

Abstract: A semiconductor package including a lower substrate, a lower semiconductor chip mounted on the lower substrate, a lower mold layer on the lower substrate and enclosing the lower semiconductor chip, a redistribution layer on the lower mold layer, and a vertical connection terminal around the lower semiconductor chip and connecting the lower substrate to the redistribution layer may be provided. The lower semiconductor chip may include a cognition mark at a top surface thereof. The cognition mark may include a marking pattern having an intaglio shape at the top surface of the lower semiconductor chip, and a molding pattern filling an inner space of the marking pattern. A first material constituting the molding pattern may be the same as a second material constituting the lower mold layer.

公开(公告)号：US20130098293A1

公开(公告)日：2013-04-25

申请号：US13655696

申请日：2012-10-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jong Hyun LEE ,  Hyun Seok RYU ,  Jung Hyun LEE ,  Ki Sung KIM ,  Suk Ho YOON ,  Young Sun KIM

IPC: C23C16/455 ,  C23C16/458

CPC classification number: C23C16/45565 ,  C23C16/45578 ,  C23C16/4558 ,  C23C16/4583 ,  H01L21/0254 ,  H01L21/02573 ,  H01L21/0262

Abstract: A chemical vapor deposition apparatus can include a reaction chamber having a reaction space therein; a wafer boat disposed in the reaction space, the wafer boat arranged and structured to support a plurality of wafers; and a gas supplying part disposed in the reaction chamber to supply two or more reaction gases to the plurality of wafers. The gas supplying part can include a plurality of gas pipes disposed in the reaction chamber to supply the two or more reaction gases from outside to the reaction space; and a plurality of supplying pipes disposed around the wafer boat, wherein each of the supplying pipes is connected to two or more corresponding gas pipes, and wherein each supplying pipe is configured to supply the two or more reaction gases supplied by the two or more corresponding gas pipes to a corresponding one of the wafers.

Abstract translation: 化学气相沉积装置可以包括其中具有反应空间的反应室; 设置在所述反应空间中的晶片舟，所述晶片舟被布置和构造为支撑多个晶片; 以及设置在所述反应室中以将多个反应气体供应到所述多个晶片的气体供给部。 气体供给部可以包括设置在反应室中的多个气体管道，用于从外部向反应空间供给两种或更多种反应气体; 以及设置在所述晶片舟周围的多个供给管，其中，所述供给管中的每一个连接到两个以上对应的气体管，并且其中每个供给管被构造成供给由所述两个或更多个相应的 将气体管道连接到相应的一个晶片。