公开(公告)号：US11908775B2

公开(公告)日：2024-02-20

申请号：US17645472

申请日：2021-12-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jaewon Hwang ,  Kwangjin Moon ,  Hojin Lee ,  Hyungjun Jeon

IPC: H01L23/48 ,  H01L23/485 ,  H01L23/535 ,  H01L23/00

CPC classification number: H01L23/485 ,  H01L23/481 ,  H01L23/535 ,  H01L24/29 ,  H01L24/45

Abstract: A semiconductor device includes a semiconductor substrate having a first surface adjacent to an active layer; a first insulating layer disposed on the first surface of the semiconductor substrate; a second insulating layer disposed on the first insulating layer; an etch stop structure interposed between the first insulating layer and the second insulating layer and including a plurality of etch stop layers; a contact wiring pattern disposed inside the second insulating layer and surrounded by at least one etch stop layer of the plurality of etch stop layers; and a through electrode structure configured to pass through the semiconductor substrate, the first insulating layer, and at least one etch stop layer of the plurality of etch stop layers in a vertical direction and contact the contact wiring pattern.

公开(公告)号：US11749586B2

公开(公告)日：2023-09-05

申请号：US17514218

申请日：2021-10-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sonkwan Hwang ,  Taeseong Kim ,  Hoonjoo Na ,  Kwangjin Moon ,  Hyungjun Jeon

IPC: H01L21/00 ,  H01L23/48 ,  H01L27/088 ,  H01L25/065 ,  H01L21/768 ,  H01L23/528 ,  H01L23/00

CPC classification number: H01L23/481 ,  H01L21/76898 ,  H01L23/528 ,  H01L25/0657 ,  H01L27/0886 ,  H01L24/02 ,  H01L24/05 ,  H01L24/06 ,  H01L2224/02381 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/05569 ,  H01L2224/0603 ,  H01L2224/06181 ,  H01L2225/06513 ,  H01L2225/06544

Abstract: A semiconductor device including a semiconductor substrate, an integrated circuit layer on the semiconductor substrate, first to nth metal wiring layers (where n is a positive integer) sequentially stacked on the semiconductor substrate and the integrated circuit layer, a first through via structure extending in a vertical direction toward the semiconductor substrate from a first via connection metal wiring layer, which is one of the second to nth metal wiring layers other than the first metal wiring layer, and passing through the semiconductor substrate, and a second through via structure being apart from the first through via structure, extending in a vertical direction toward the semiconductor substrate from a second via connection metal wiring layer, which is one of the second to nth metal wiring layers other than the first metal wiring layer, and passing through the semiconductor substrate may be provided.

公开(公告)号：US20230335415A1

公开(公告)日：2023-10-19

申请号：US18337202

申请日：2023-06-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyungjun Jeon ,  Taeyeong Kim ,  Hoechul Kim ,  Junhong Min

IPC: H01L21/67 ,  H01L23/00 ,  B32B37/00 ,  B32B41/00

CPC classification number: H01L21/67017 ,  H01L24/74 ,  H01L21/67092 ,  B32B37/0046 ,  B32B37/003 ,  B32B41/00 ,  B32B2457/14 ,  H01L21/68742

Abstract: A bonding method for bonding a first substrate to a second substrate includes fixing the first substrate to a first surface of a first bonding chuck and fixing the second substrate to a second surface of a second bonding chuck, the second surface facing the first surface; aligning the second bonding chuck above the first bonding chuck in a vertical direction or in a horizontal direction; bonding the first substrate to the second substrate to make a bonded substrate; and wherein, in the bonding the first substrate to the second substrate, injecting a process gas between the first substrate and the second substrate using a process gas injector surrounding at least one selected from the first bonding chuck and the second bonding chuck in a plan view and injecting an air curtain forming gas to form an air curtain surrounding the first substrate and the second substrate using an air curtain generator are performed in combination.

公开(公告)号：US20220013503A1

公开(公告)日：2022-01-13

申请号：US17209801

申请日：2021-03-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Eunsuk Jung ,  Hyoukyung Cho ,  Jinnam Kim ,  Hyungjun Jeon ,  Kwangjin Moon ,  Hoonjoo Na ,  Hakseung Lee

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/31

Abstract: A semiconductor package includes first to fourth semiconductor chips sequentially stacked on one another. A backside of a third substrate of the third semiconductor chip may be arranged to face a backside surface of a second substrate of the second semiconductor chip such that the third substrate and a second backside insulation layer provided on the backside surface of the second substrate are bonded directly to each other, or the backside of the third substrate may be arranged to face a front surface of the second substrate such that the third substrate and a second front insulation layer provided on the front surface of the second substrate are bonded directly to each other.

公开(公告)号：US12300671B2

公开(公告)日：2025-05-13

申请号：US18487247

申请日：2023-10-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Eunsuk Jung ,  Hyoukyung Cho ,  Jinnam Kim ,  Hyungjun Jeon ,  Kwangjin Moon ,  Hoonjoo Na ,  Hakseung Lee

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/31

Abstract: A semiconductor package includes first to fourth semiconductor chips sequentially stacked on one another. A backside of a third substrate of the third semiconductor chip may be arranged to face a backside surface of a second substrate of the second semiconductor chip such that the third substrate and a second backside insulation layer provided on the backside surface of the second substrate are bonded directly to each other, or the backside of the third substrate may be arranged to face a front surface of the second substrate such that the third substrate and a second front insulation layer provided on the front surface of the second substrate are bonded directly to each other.

公开(公告)号：US20240153851A1

公开(公告)日：2024-05-09

申请号：US18406602

申请日：2024-01-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JAEWON HWANG ,  Kwangjin Moon ,  Hojin Lee ,  Hyungjun Jeon

IPC: H01L23/485 ,  H01L23/00 ,  H01L23/48 ,  H01L23/535

CPC classification number: H01L23/485 ,  H01L23/481 ,  H01L23/535 ,  H01L24/29 ,  H01L24/45

Abstract: A semiconductor device includes a semiconductor substrate having a first surface adjacent to an active layer; a first insulating layer disposed on the first surface of the semiconductor substrate; a second insulating layer disposed on the first insulating layer; an etch stop structure interposed between the first insulating layer and the second insulating layer and including a plurality of etch stop layers; a contact wiring pattern disposed inside the second insulating layer and surrounded by at least one etch stop layer of the plurality of etch stop layers; and a through electrode structure configured to pass through the semiconductor substrate, the first insulating layer, and at least one etch stop layer of the plurality of etch stop layers in a vertical direction and contact the contact wiring pattern.

公开(公告)号：US11810900B2

公开(公告)日：2023-11-07

申请号：US17209801

申请日：2021-03-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Eunsuk Jung ,  Hyoukyung Cho ,  Jinnam Kim ,  Hyungjun Jeon ,  Kwangjin Moon ,  Hoonjoo Na ,  Hakseung Lee

IPC: H01L25/065 ,  H01L23/31 ,  H01L23/00

CPC classification number: H01L25/0657 ,  H01L23/3128 ,  H01L24/08 ,  H01L2224/08146

Abstract: A semiconductor package includes first to fourth semiconductor chips sequentially stacked on one another. A backside of a third substrate of the third semiconductor chip may be arranged to face a backside surface of a second substrate of the second semiconductor chip such that the third substrate and a second backside insulation layer provided on the backside surface of the second substrate are bonded directly to each other, or the backside of the third substrate may be arranged to face a front surface of the second substrate such that the third substrate and a second front insulation layer provided on the front surface of the second substrate are bonded directly to each other.

公开(公告)号：US11315894B2

公开(公告)日：2022-04-26

申请号：US17035215

申请日：2020-09-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyungjun Jeon ,  Kwangjin Moon ,  Hakseung Lee ,  Hyoukyung Cho

IPC: H01L25/065 ,  H01L23/00 ,  H01L21/683 ,  H01L21/78 ,  H01L25/00

Abstract: A semiconductor stack and a method for manufacturing the same are disclosed. The semiconductor stack includes a lower chip, an upper chip disposed over the lower chip, an upper lateral-side passivation layer surrounding side surfaces of the upper chip, and a plurality of bonding pads and a bonding passivation layer disposed between the upper chip and the lower chip.

公开(公告)号：US20210143026A1

公开(公告)日：2021-05-13

申请号：US17014335

申请日：2020-09-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyungjun Jeon ,  Taeyeong Kim ,  Hoechul Kim ,  Junhong Min

IPC: H01L21/67 ,  H01L23/00 ,  B32B37/00 ,  B32B41/00

Abstract: A substrate bonding apparatus for bonding a first substrate to a second substrate includes a first bonding chuck configured to fix the first substrate to a first surface of the first bonding chuck; a second bonding chuck configured to fix the second substrate to a second surface of the second bonding chuck, the second surface facing the first surface; a process gas injector surrounding at least one selected from the first bonding chuck and the second bonding chuck in a plan view, the process gas injector configured to inject a process gas between the first substrate and the second substrate when respectively disposed on the first bonding chuck and the second bonding chuck; and an air curtain generator disposed at an outside of the process gas injector in the plan view, the air curtain generator configured to inject an air curtain forming gas to form an air curtain surrounding the first substrate and the second substrate.

公开(公告)号：US12046538B2

公开(公告)日：2024-07-23

申请号：US18354068

申请日：2023-07-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sonkwan Hwang ,  Taeseong Kim ,  Hoonjoo Na ,  Kwangjin Moon ,  Hyungjun Jeon

IPC: H01L21/00 ,  H01L21/768 ,  H01L23/48 ,  H01L23/528 ,  H01L25/065 ,  H01L27/088 ,  H01L23/00

CPC classification number: H01L23/481 ,  H01L21/76898 ,  H01L23/528 ,  H01L25/0657 ,  H01L27/0886 ,  H01L24/02 ,  H01L24/05 ,  H01L24/06 ,  H01L2224/02381 ,  H01L2224/0401 ,  H01L2224/05569 ,  H01L2224/0557 ,  H01L2224/0603 ,  H01L2224/06181 ,  H01L2225/06513 ,  H01L2225/06544

Abstract: A semiconductor device including a semiconductor substrate, an integrated circuit layer on the semiconductor substrate, first to nth metal wiring layers (where n is a positive integer) sequentially stacked on the semiconductor substrate and the integrated circuit layer, a first through via structure extending in a vertical direction toward the semiconductor substrate from a first via connection metal wiring layer, which is one of the second to nth metal wiring layers other than the first metal wiring layer, and passing through the semiconductor substrate, and a second through via structure being apart from the first through via structure, extending in a vertical direction toward the semiconductor substrate from a second via connection metal wiring layer, which is one of the second to nth metal wiring layers other than the first metal wiring layer, and passing through the semiconductor substrate may be provided.