公开(公告)号：US20220013503A1

公开(公告)日：2022-01-13

申请号：US17209801

申请日：2021-03-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Eunsuk Jung ,  Hyoukyung Cho ,  Jinnam Kim ,  Hyungjun Jeon ,  Kwangjin Moon ,  Hoonjoo Na ,  Hakseung Lee

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/31

Abstract: A semiconductor package includes first to fourth semiconductor chips sequentially stacked on one another. A backside of a third substrate of the third semiconductor chip may be arranged to face a backside surface of a second substrate of the second semiconductor chip such that the third substrate and a second backside insulation layer provided on the backside surface of the second substrate are bonded directly to each other, or the backside of the third substrate may be arranged to face a front surface of the second substrate such that the third substrate and a second front insulation layer provided on the front surface of the second substrate are bonded directly to each other.

公开(公告)号：US11694980B2

公开(公告)日：2023-07-04

申请号：US17709856

申请日：2022-03-31

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyungjun Jeon ,  Kwangjin Moon ,  Hakseung Lee ,  Hyoukyung Cho

IPC: H01L21/683 ,  H01L23/00 ,  H01L25/065 ,  H01L21/78 ,  H01L25/00

CPC classification number: H01L24/08 ,  H01L21/6835 ,  H01L21/78 ,  H01L24/80 ,  H01L25/0657 ,  H01L25/50 ,  H01L2221/68327 ,  H01L2224/08145 ,  H01L2224/80006 ,  H01L2224/80895 ,  H01L2224/80896

Abstract: A semiconductor stack and a method for manufacturing the same are disclosed. The semiconductor stack includes a lower chip, an upper chip disposed over the lower chip, an upper lateral-side passivation layer surrounding side surfaces of the upper chip, and a plurality of bonding pads and a bonding passivation layer disposed between the upper chip and the lower chip.

公开(公告)号：US20210005533A1

公开(公告)日：2021-01-07

申请号：US16750579

申请日：2020-01-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyoukyung Cho ,  Daesuk Lee ,  Jinnam Kim ,  Taeseong Kim ,  Kwangjin Moon ,  Hakseung Lee

IPC: H01L23/48 ,  H01L23/528 ,  H01L23/00 ,  H01L25/065 ,  H01L23/532 ,  H01L21/768 ,  H01L21/02 ,  H01L21/306

Abstract: Disclosed are semiconductor packages and methods of fabricating the same. The semiconductor package comprises a first wiring layer, a first semiconductor substrate on the first wiring layer, a first dielectric layer on the first semiconductor substrate, a landing pad in the first wiring layer, a through hole that penetrates the first semiconductor substrate, the first dielectric layer, and the first wiring layer and exposes the landing pad, the through hole including a first hole and a second hole on a bottom end of the first hole, the second hole having a maximum diameter less than a minimum diameter of the first hole, and a mask layer on an upper lateral surface of the through hole.

公开(公告)号：US11373932B2

公开(公告)日：2022-06-28

申请号：US16750579

申请日：2020-01-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyoukyung Cho ,  Daesuk Lee ,  Jinnam Kim ,  Taeseong Kim ,  Kwangjin Moon ,  Hakseung Lee

IPC: H01L23/48 ,  H01L23/00 ,  H01L25/065 ,  H01L23/532 ,  H01L21/768 ,  H01L21/02 ,  H01L21/306 ,  H01L23/528 ,  H01L21/027 ,  H01L21/288 ,  H01L21/321

Abstract: Disclosed are semiconductor packages and methods of fabricating the same. The semiconductor package comprises a first wiring layer, a first semiconductor substrate on the first wiring layer, a first dielectric layer on the first semiconductor substrate, a landing pad in the first wiring layer, a through hole that penetrates the first semiconductor substrate, the first dielectric layer, and the first wiring layer and exposes the landing pad, the through hole including a first hole and a second hole on a bottom end of the first hole, the second hole having a maximum diameter less than a minimum diameter of the first hole, and a mask layer on an upper lateral surface of the through hole.

公开(公告)号：US20210043575A1

公开(公告)日：2021-02-11

申请号：US16849085

申请日：2020-04-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hakseung Lee ,  Jinnam Kim ,  Hyoukyung Cho ,  Taeseong Kim ,  Kwangjin Moon

IPC: H01L23/538

Abstract: A semiconductor device may include a first semiconductor substrate having a first surface and a second surface opposite to each other, a first circuit layer provided on the first surface of the first semiconductor substrate, a connection pad provided on the second surface of the first semiconductor substrate, and a first penetration via and a second penetration via penetrating the first semiconductor substrate and at least a portion of the first circuit layer. The first penetration via and the second penetration via may be provided in a first penetration hole and a second penetration hole, respectively. Each of the first and second penetration holes may include a first portion, a second portion, and a third portion. A width of the first portion of the first penetration hole may be smaller than a width of the first portion of the second penetration hole.

公开(公告)号：US11961788B2

公开(公告)日：2024-04-16

申请号：US17708137

申请日：2022-03-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyoukyung Cho ,  Hojin Lee ,  Kwangjin Moon

IPC: H01L23/48 ,  H01L21/762 ,  H01L21/768 ,  H01L25/065 ,  H01L29/06

CPC classification number: H01L23/481 ,  H01L21/76224 ,  H01L21/76816 ,  H01L21/76898 ,  H01L25/0657 ,  H01L29/0649 ,  H01L2225/06544

Abstract: A semiconductor device includes: a semiconductor substrate having opposing first side and second sides; an active region and an isolation region on the first side; a circuit device on the active region; a front side interconnection structure on the first side and including front side interconnection layers disposed on different levels; first and second back side interconnection structures below the second side; a buried structure having a portion disposed in the isolation region and including a conductive line; a first through-electrode structure including a first through-electrode contacting the conductive line and penetrating the semiconductor substrate between the conductive line and the first back side interconnection structure; and a second through-electrode structure including a second through-electrode penetrating the semiconductor substrate between a first front side interconnection layer and the second back side interconnection structure. The first front side interconnection layer is on a level higher than that of the conductive line.

公开(公告)号：US20240038732A1

公开(公告)日：2024-02-01

申请号：US18487247

申请日：2023-10-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Eunsuk Jung ,  Hyoukyung Cho ,  Jinnam Kim ,  Hyungjun Jeon ,  Kwangjin Moon ,  Hoonjoo Na ,  Hakseung Lee

IPC: H01L25/065 ,  H01L23/31 ,  H01L23/00

CPC classification number: H01L25/0657 ,  H01L23/3128 ,  H01L24/08 ,  H01L2224/08146

Abstract: A semiconductor package includes first to fourth semiconductor chips sequentially stacked on one another. A backside of a third substrate of the third semiconductor chip may be arranged to face a backside surface of a second substrate of the second semiconductor chip such that the third substrate and a second backside insulation layer provided on the backside surface of the second substrate are bonded directly to each other, or the backside of the third substrate may be arranged to face a front surface of the second substrate such that the third substrate and a second front insulation layer provided on the front surface of the second substrate are bonded directly to each other.

公开(公告)号：US11804419B2

公开(公告)日：2023-10-31

申请号：US17185166

申请日：2021-02-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hakseung Lee ,  Kwangjin Moon ,  Hyungjun Jeon ,  Hyoukyung Cho

IPC: H01L23/48 ,  H01L23/522 ,  H01L23/00 ,  H01L23/528 ,  H01L25/065

CPC classification number: H01L23/481 ,  H01L23/5226 ,  H01L23/5283 ,  H01L24/08 ,  H01L25/0652 ,  H01L2224/08146

Abstract: A semiconductor device may include a substrate including a first surface and a second surface, which are opposite to each other, an insulating layer on the first surface of the substrate, a first via structure and a second via structure penetrating the substrate and a portion of the insulating layer and having different widths from each other in a direction parallel to the first surface of the substrate, metal lines provided in the insulating layer, and an integrated circuit provided on the first surface of the substrate. A bottom surface of the first via structure may be located at a level lower than a bottom surface of the second via structure, when measured from the first surface of the substrate. The second via structure may be electrically connected to the integrated circuit through the metal lines.

公开(公告)号：US12300671B2

公开(公告)日：2025-05-13

申请号：US18487247

申请日：2023-10-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Eunsuk Jung ,  Hyoukyung Cho ,  Jinnam Kim ,  Hyungjun Jeon ,  Kwangjin Moon ,  Hoonjoo Na ,  Hakseung Lee

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/31

Abstract: A semiconductor package includes first to fourth semiconductor chips sequentially stacked on one another. A backside of a third substrate of the third semiconductor chip may be arranged to face a backside surface of a second substrate of the second semiconductor chip such that the third substrate and a second backside insulation layer provided on the backside surface of the second substrate are bonded directly to each other, or the backside of the third substrate may be arranged to face a front surface of the second substrate such that the third substrate and a second front insulation layer provided on the front surface of the second substrate are bonded directly to each other.

公开(公告)号：US11810900B2

公开(公告)日：2023-11-07

申请号：US17209801

申请日：2021-03-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Eunsuk Jung ,  Hyoukyung Cho ,  Jinnam Kim ,  Hyungjun Jeon ,  Kwangjin Moon ,  Hoonjoo Na ,  Hakseung Lee

IPC: H01L25/065 ,  H01L23/31 ,  H01L23/00

CPC classification number: H01L25/0657 ,  H01L23/3128 ,  H01L24/08 ,  H01L2224/08146

Abstract: A semiconductor package includes first to fourth semiconductor chips sequentially stacked on one another. A backside of a third substrate of the third semiconductor chip may be arranged to face a backside surface of a second substrate of the second semiconductor chip such that the third substrate and a second backside insulation layer provided on the backside surface of the second substrate are bonded directly to each other, or the backside of the third substrate may be arranged to face a front surface of the second substrate such that the third substrate and a second front insulation layer provided on the front surface of the second substrate are bonded directly to each other.