公开(公告)号：US20230209808A1

公开(公告)日：2023-06-29

申请号：US17880723

申请日：2022-08-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ahrang Choi ,  Chansic Yoon ,  Hoin Ryu ,  Junghoon Han

IPC: H01L27/108

CPC classification number: H01L27/10823 ,  H01L27/10814

Abstract: A semiconductor device includes active regions defined by a device isolation region in a substrate; trenches extending in a first direction to intersect the active regions; buried gate structures buried in the trenches, respectively, and having upper surfaces located on a level lower than a level of upper surfaces of the active regions; a buffer structure covering the active regions, the isolation region, and the buried gate structures; bit line structures extending in a second direction intersecting the first direction on the active regions and connected to the active regions; storage node contacts between the bit line structures, penetrating through the buffer structure and in contact with the active regions; and capacitor structures in contact with an upper surface of the storage node contacts.

公开(公告)号：US20240155836A1

公开(公告)日：2024-05-09

申请号：US18492821

申请日：2023-10-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Joonyoung Kang ,  Hoju Song ,  Kanguk Kim ,  Seokhyun Kim ,  Youngjun Kim ,  Jooncheol Kim ,  Jinwoong Kim ,  Hoin Ryu ,  Hyeran Lee

IPC: H10B12/00

CPC classification number: H10B12/485 ,  H10B12/02 ,  H10B12/315 ,  H10B12/34 ,  H10B12/482

Abstract: Semiconductor devices may include: a substrate including a plurality of active areas defined by a device isolation layer; a plurality of bit lines extending on the substrate in a first horizontal direction; a plurality of insulation fences that are spaced apart from each other in the first horizontal direction in a space between two adjacent bit lines among the plurality of bit lines on the substrate; a plurality of buried contacts that are between the adjacent two bit lines among the plurality of bit lines and are arranged alternately with the plurality of insulation fences along the first horizontal direction on the substrate, the plurality of buried contacts being connected to the plurality of active areas, respectively; and a plurality of insulating layer, each of which is between a respective one of the plurality of insulation fences and a respective one of the plurality of buried contacts.

公开(公告)号：US20230247825A1

公开(公告)日：2023-08-03

申请号：US17970799

申请日：2022-10-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyeonok Jung ,  Donghwa Shin ,  Hoin Ryu ,  Youngseung Cho

IPC: H01L27/108

CPC classification number: H01L27/10897 ,  H01L27/10814

Abstract: A semiconductor device may include a substrate extending in a first direction and a second direction perpendicular to the first direction, the substrate including a memory cell region, a peripheral circuit region, and a boundary region between the memory cell region and the peripheral circuit region, first active patterns in the memory cell region, each of the first active patterns extending in a third direction oblique to the first direction, and a silicon dam structure in the boundary region. The silicon dam structure may include a silicon dam pattern including trench lines extending in the oblique direction and a dam isolation pattern in the trench lines.