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公开(公告)号：US11925020B2
公开(公告)日：2024-03-05
申请号：US17473006
申请日：2021-09-13
Applicant: Samsung Electronics Co., Ltd.
Inventor： Shinhwan Kang , Younghwan Son , Haemin Lee , Kohji Kanamori , Jeehoon Han
Abstract: A vertical semiconductor device may include a stacked structure and a plurality of channel structures. The stacked structure may include insulation layers and gate patterns alternately and repeatedly stacked on a substrate. The stacked structure may extend in a first direction parallel to an upper surface of the substrate. The gate patterns may include at least ones of first gate patterns. The stacked structure may include a sacrificial pattern between the first gate patterns. The channel structures may pass through the stacked structure. Each of the channel structures may extend to the upper surface of the substrate, and each of the channel structures may include a charge storage structure and a channel. Ones of the channel structures may pass through the sacrificial pattern in the stacked structure to the upper surface of the substrate, and may extend to the upper surface of the substrate.
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公开(公告)号：US11800712B2
公开(公告)日：2023-10-24
申请号：US17339129
申请日：2021-06-04
Applicant: Samsung Electronics Co., Ltd.
Inventor： Juyeon Jung , Kwanyong Kim , Haemin Lee , Juyoung Lim , Wonseok Cho
IPC: H01L27/11582 , H10B43/27 , H10B41/10 , H10B41/27 , H10B41/35 , H10B41/40 , H10B43/10 , H10B43/35 , H10B43/40
CPC classification number: H10B43/27 , H10B41/10 , H10B41/27 , H10B41/35 , H10B41/40 , H10B43/10 , H10B43/35 , H10B43/40
Abstract: A semiconductor memory device includes a substrate having a first region, a second region, and a third region main separation regions extending in the first direction and apart from each other in a second direction, first auxiliary separation regions extending in the first direction and spaced apart from each other in the second direction, and second auxiliary separation regions extending in the first direction and spaced apart from each other in the second direction. The first auxiliary separation regions are at a first pitch in the second direction between the main separation regions, the second auxiliary separation regions are disposed at a second pitch, smaller than the first pitch in the second direction between the main separation regions, and the first auxiliary separation regions and the second auxiliary separation regions are shifted from each other in the second direction.
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公开(公告)号：US20220208789A1
公开(公告)日：2022-06-30
申请号：US17528233
申请日：2021-11-17
Applicant: Samsung Electronics Co., Ltd.
Inventor： Haemin Lee , Jongsoo Kim , Hyeonjoo Song , Juyeon Jung
IPC: H01L27/11582 , H01L27/1157 , H01L27/11573 , H01L27/11565 , H01L27/11556 , H01L27/11524 , H01L27/11526 , H01L27/11519 , H01L23/528
Abstract: A semiconductor device comprises a stack structure including interlayer insulating layers and gate layers alternately stacked on a lower structure; and a memory vertical structure, separation structures, and support vertical structures penetrating the stack structure, wherein the gate layers include a lower gate layer, an upper gate layer, and intermediate gate layers, wherein the separation structures include a first separation structure, wherein the support vertical structures include a first inner support vertical structure penetrating the lower gate layer, the intermediate gate layers, and the upper gate layer, and adjacent to the first separation structure, wherein a portion of the first inner support vertical structure is directly connected to the first separation structure on the same level as the upper gate layer, and wherein a portion of the first inner support vertical structure is spaced apart from the first separation structure on the same level as the lower gate layer.
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公开(公告)号：US20250056803A1
公开(公告)日：2025-02-13
申请号：US18931231
申请日：2024-10-30
Applicant: Samsung Electronics Co., Ltd
Inventor： Haemin Lee , Jongsoo Kim , Hyeonjoo Song , Juyeon Jung
IPC: H10B43/27 , H01L23/528 , H10B41/10 , H10B41/27 , H10B41/35 , H10B41/40 , H10B43/10 , H10B43/35 , H10B43/40
Abstract: A semiconductor device comprises a stack structure including interlayer insulating layers and gate layers alternately stacked on a lower structure; and a memory vertical structure, separation structures, and support vertical structures penetrating the stack structure, wherein the gate layers include a lower gate layer, an upper gate layer, and intermediate gate layers, wherein the separation structures include a first separation structure, wherein the support vertical structures include a first inner support vertical structure penetrating the lower gate layer, the intermediate gate layers, and the upper gate layer, and adjacent to the first separation structure, wherein a portion of the first inner support vertical structure is directly connected to the first separation structure on the same level as the upper gate layer, and wherein a portion of the first inner support vertical structure is spaced apart from the first separation structure on the same level as the lower gate layer.
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公开(公告)号：US12160991B2
公开(公告)日：2024-12-03
申请号：US17528233
申请日：2021-11-17
Applicant: Samsung Electronics Co., Ltd.
Inventor： Haemin Lee , Jongsoo Kim , Hyeonjoo Song , Juyeon Jung
IPC: H10B43/27 , H01L23/528 , H10B41/10 , H10B41/27 , H10B41/35 , H10B41/40 , H10B43/10 , H10B43/35 , H10B43/40
Abstract: A semiconductor device comprises a stack structure including interlayer insulating layers and gate layers alternately stacked on a lower structure; and a memory vertical structure, separation structures, and support vertical structures penetrating the stack structure, wherein the gate layers include a lower gate layer, an upper gate layer, and intermediate gate layers, wherein the separation structures include a first separation structure, wherein the support vertical structures include a first inner support vertical structure penetrating the lower gate layer, the intermediate gate layers, and the upper gate layer, and adjacent to the first separation structure, wherein a portion of the first inner support vertical structure is directly connected to the first separation structure on the same level as the upper gate layer, and wherein a portion of the first inner support vertical structure is spaced apart from the first separation structure on the same level as the lower gate layer.
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Patent Agency Ranking
公开(公告)号：US11121151B2
公开(公告)日：2021-09-14
申请号：US16562919
申请日：2019-09-06
Applicant: Samsung Electronics Co., Ltd.
Inventor： Shinhwan Kang , Younghwan Son , Haemin Lee , Kohji Kanamori , Jeehoon Han
IPC: H01L27/00 , H01L27/11582 , H01L27/11565 , H01L27/11519 , H01L27/11556 , H01L27/1157
Abstract: A vertical semiconductor device may include a stacked structure and a plurality of channel structures. The stacked structure may include insulation layers and gate patterns alternately and repeatedly stacked on a substrate. The stacked structure may extend in a first direction parallel to an upper surface of the substrate. The gate patterns may include at least ones of first gate patterns. The stacked structure may include a sacrificial pattern between the first gate patterns. The channel structures may pass through the stacked structure. Each of the channel structures may extend to the upper surface of the substrate, and each of the channel structures may include a charge storage structure and a channel. Ones of the channel structures may pass through the sacrificial pattern in the stacked structure to the upper surface of the substrate, and may extend to the upper surface of the substrate.
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7.发明授权公开(公告)号：US12261120B2
公开(公告)日：2025-03-25
申请号：US17391445
申请日：2021-08-02
Applicant: Samsung Electronics Co., Ltd.
Inventor： Haemin Lee
IPC: H01L23/535 , H10B41/27 , H10B41/41 , H10B43/27 , H10B43/40
Abstract: A 3D semiconductor memory device includes a peripheral circuit structure, an intermediate insulating layer and a cell array structure. The cell array structure includes a first substrate including a cell array region and a connection region; a stack structure comprising electrode layers and electrode interlayer insulating layers alternately stacked on the first substrate; a planarization insulating layer covering an end portion of the stack structure on the connection region; and a first through-via penetrating the planarization insulating layer, the first substrate and the intermediate insulating layer. The first through-via connects one of the electrode layers to the peripheral circuit structure. The first through-via includes a first and second via portion integrally connected to each other. The first via portion penetrates the planarization insulating layer and has a first width. The second via portion penetrates the intermediate insulating layer and has a second width greater than the first width.
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公开(公告)号：US12075622B2
公开(公告)日：2024-08-27
申请号：US17465928
申请日：2021-09-03
Applicant: Samsung Electronics Co., Ltd.
Inventor： Hyeonjoo Song , Haemin Lee
IPC: H10B43/27 , H01L23/48 , H10B41/10 , H10B41/27 , H10B41/35 , H10B41/40 , H10B43/10 , H10B43/35 , H10B43/40
CPC classification number: H10B43/27 , H01L23/481 , H10B41/10 , H10B41/27 , H10B41/35 , H10B41/40 , H10B43/10 , H10B43/35 , H10B43/40
Abstract: Integrated circuit devices may include: a gate stack extending on a substrate in a first direction that may be parallel to a main surface of the substrate, the gate stack including a plurality of gate electrodes overlapping each other in a vertical direction that may be perpendicular to the main surface of the substrate; a channel structure extending through the gate stack and extending in the vertical direction; a word line cut opening extending through the gate stack in the vertical direction and extending in the first direction; and an upper support layer on the gate stack and including a hole overlapping the word line cut opening in the vertical direction. An upper surface of the channel structure is in contact with a lower surface of the upper support layer.
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公开(公告)号：US11450681B2
公开(公告)日：2022-09-20
申请号：US16844234
申请日：2020-04-09
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Haemin Lee , Jongwon Kim , Shinhwan Kang , Kohji Kanamori , Jeehoon Han
IPC: H01L27/1157 , H01L27/11556 , H01L27/11521 , H01L27/11578
Abstract: A semiconductor device includes a first stack group having first interlayer insulating layers and first gate layers, alternately and repeatedly stacked on a substrate and a second stack group comprising second interlayer insulating layers and second gate layers, alternately and repeatedly stacked on the first stack group. Separation structures pass through the first and second stack groups and include a first separation region and a second separation region. A vertical structure passes through the first and second stack groups and includes a first vertical region and a second vertical region. A conductive line is electrically connected to the vertical structure on the second stack group. A distance between an upper end of the first vertical region and an upper surface of the substrate is greater than a distance between an upper end of the first separation region and an upper surface of the substrate.
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公开(公告)号：US11974438B2
公开(公告)日：2024-04-30
申请号：US17903315
申请日：2022-09-06
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Haemin Lee , Jongwon Kim , Shinhwan Kang , Kohji Kanamori , Jeehoon Han
Abstract: A semiconductor device includes a first stack group having first interlayer insulating layers and first gate layers, alternately and repeatedly stacked on a substrate and a second stack group comprising second interlayer insulating layers and second gate layers, alternately and repeatedly stacked on the first stack group. Separation structures pass through the first and second stack groups and include a first separation region and a second separation region. A vertical structure passes through the first and second stack groups and includes a first vertical region and a second vertical region. A conductive line is electrically connected to the vertical structure on the second stack group. A distance between an upper end of the first vertical region and an upper surface of the substrate is greater than a distance between an upper end of the first separation region and an upper surface of the substrate.
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