公开(公告)号：US20240215249A1

公开(公告)日：2024-06-27

申请号：US18322365

申请日：2023-05-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyunghun KIM ,  Sunho KIM ,  Seyun KIM ,  Hyungyung KIM ,  Seungyeul YANG ,  Gukhyon YON ,  Minhyun LEE ,  Seokhoon CHOI ,  Hoseok HEO

IPC: H10B43/35 ,  H10B43/27

CPC classification number: H10B43/35 ,  H10B43/27

Abstract: A vertical NAND flash memory device may include a plurality of cell arrays. Each of the plurality of cell arrays may include a channel layer, a charge trap layer on the channel layer, and a plurality of gate electrodes on the charge trap layer. The charge trap layer may include silicon oxynitride comprising a metal. The metal may include at least one of Ga or In.

公开(公告)号：US20240224530A1

公开(公告)日：2024-07-04

申请号：US18215533

申请日：2023-06-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seungdam HYUN ,  Kyunghun KIM ,  Sunho KIM ,  Hyungyung KIM ,  Kwangmin PARK ,  Seungyeul YANG ,  Gukhyon YON ,  Minhyun LEE ,  Seokhoon CHOI ,  Hoseok HEO

IPC: H10B43/35 ,  G11C16/04 ,  H01L29/423 ,  H10B43/10 ,  H10B43/27

CPC classification number: H10B43/35 ,  G11C16/0483 ,  H01L29/4234 ,  H10B43/10 ,  H10B43/27

Abstract: A vertical NAND flash memory device includes a plurality of cell arrays, where each cell array of the plurality of cell arrays includes a channel layer, a charge trap layer provided on the channel layer, the charge trap layer including a matrix comprising a dielectric and a charge trap material in the matrix and including anti-ferroelectric nanocrystals or ferroelectric nanocrystals, and a plurality of gate electrodes provided on the charge trap layer.

公开(公告)号：US20240221834A1

公开(公告)日：2024-07-04

申请号：US18357407

申请日：2023-07-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hoseok HEO ,  Hyungyung KIM ,  Seungdam HYUN ,  Kyunghun KIM ,  Seungyeul YANG ,  Gukhyon YON ,  Minhyun LEE ,  Seokhoon CHOI

IPC: G11C16/04 ,  H10B43/27

CPC classification number: G11C16/0483 ,  H10B43/27

Abstract: A vertical non-volatile memory device and an electronic apparatus including the vertical non-volatile memory device are provided. The vertical non-volatile memory device includes a pillar, a channel layer surrounding a side surface of the pillar, a charge tunneling layer surrounding a side surface of the channel layer, a charge trap layer surrounding a side surface of the charge tunneling layer and including an amorphous oxynitride, a charge blocking layer surrounding a side surface of the charge trap layer, and a plurality of separation layers and a plurality of gate electrodes surrounding a side surface of the charge blocking layer and alternately arranged along the side surface of the charge blocking layer.

公开(公告)号：US20200340115A1

公开(公告)日：2020-10-29

申请号：US16590975

申请日：2019-10-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sangyub IE ,  Gukhyon YON

IPC: C23C16/455 ,  H01L21/02 ,  C23C16/52 ,  C23C16/48 ,  H01L21/687

Abstract: An atomic layer deposition (ALD) apparatus includes a light source disposed at an upper portion of a section, a wafer supporting part disposed at a lower portion of the section, and a lens pocket between the light source and the wafer supporting part, and including a frame part and a transparent panel, the lens pocket including a pocket space having sides defined by the frame part and a bottom defined by the transparent panel.

公开(公告)号：US20230247834A1

公开(公告)日：2023-08-03

申请号：US17986983

申请日：2022-11-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Soyeong AHN ,  Gukhyon YON

IPC: H01L27/11582 ,  H01L27/11556 ,  H01L27/11529 ,  H01L27/11573

CPC classification number: H01L27/11582 ,  H01L27/11556 ,  H01L27/11529 ,  H01L27/11573

Abstract: Disclosed are a three-dimensional semiconductor memory device, an electronic system including the same, and a method of fabricating the same. The semiconductor memory device may include a stack structure including electrode layers and electrode interlayer insulating layers, which are alternately stacked on a substrate, vertical semiconductor penetrating the stack structure and placed adjacent to the substrate, and a gate insulating layer between the vertical semiconductor patterns and the stack structure. The gate insulating layer may include a blocking insulating layer adjacent to the stack structure, and charge storing patterns, which are spaced apart from the stack structure with the blocking insulating layer therebetween and are arranged along a surface of the blocking insulating layer. As a distance to the blocking insulating layer decreases, widths of the charge storing patterns may increase.

公开(公告)号：US20220320135A1

公开(公告)日：2022-10-06

申请号：US17537984

申请日：2021-11-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Youngtek OH ,  Hyeyoung KWON ,  Taein KIM ,  Gukhyon YON ,  Minhyun LEE

IPC: H01L27/11582

Abstract: A nonvolatile memory device includes a channel layer, a plurality of gate electrodes and a plurality of separation layers spaced apart from the channel layer and alternately arranged, a charge trap layer between the gate electrodes in the channel layer, and a charge blocking layer between the charge trap layer and the gate electrode.